Building 3D-ICs: Tool Flow and Design Software (Part 1)
Robert Patti, Tezzaron Semiconductor
EETimes (11/14/2011 11:23 AM EST)
The industry’s current enthusiasm for 3D-ICs is widespread and well warranted, but designing those 3D devices presents a challenge. Normal 2D tool flows, thoroughly honed and refined over many years, nonetheless fail to address some of the critical issues of 3D design. A new 3D design process is evolving gradually from that 2D heritage. When Tezzaron designed its first 3D circuits in 2003, the designers used standard 2D CAD tools and cobbled together a 3D DRC and LVS flow based on scripts. Today there are tools to handle a complete backend flow and strides are being made to enable true 3D design partitioning, synthesis, placement, and routing.
This article discusses the current state of 3D tools and software, describes a working flow, and identifies the areas where more progress is needed. We base the discussion on a specific next-generation demonstration device taken from a design that Tezzaron is prototyping with several partners. The demo design contains an advanced ARM® processor stack, an “off the shelf” FPGA die, and a DRAM memory stack, all assembled onto an active silicon circuit board acting as an interposer.
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