Four ways to build a CAD flow: In-house design to custom-EDA tool
By Daniel Hoggar, Verific Design Automation
EDN (June 9, 2022)
An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
And yet, every semiconductor project group deals with inefficiencies that constrain them from delivering ideal solutions and limits productivity. Today’s CAD engineers use a patchwork of tools, flows and scripts consisting of commercial electronic design automation (EDA) products, commercial or in-house customized add-ons and in-house intellectual property (IP), a problem for many project groups because of:
- Tool flow gaps in existing EDA products
- The burden of maintaining in-house or homegrown tools, flows and scripts
- The lack of time to build and test high-quality, robust internal tools
That inevitably leads to a bunch of problems, as explained in the following sections.
To read the full article, click here
Related Semiconductor IP
- Zigbee Transceiver PHY
- Data Flow Architecture IP
- AMBA SPI Controller MRAM Controller
- Ethernet MAC
- Protocol Bridges
Related Articles
- BCD Technology: A Unified Approach to Analog, Digital, and Power Design
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Automotive Design Needs Efficient Verification to Survive
- Vital Ways to Prevent a Cyberattack
Latest Articles
- A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
- BitFair: A 12nm Bit-Serial CNN Accelerator with Learnable Early Termination and Adaptive Bit Ordering for Ultra-Low-Power XR Vision
- A Flexible Sparsity-Aware FPGA Accelerator with Column-Wise Compression for Efficient CNN Inference
- Reducing Instruction-Fetch Energy in RISC-V for Embedded AI Processing via Dynamic and Static Loop Caching
- SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow