Four ways to build a CAD flow: In-house design to custom-EDA tool
By Daniel Hoggar, Verific Design Automation
EDN (June 9, 2022)
An internal computer aided design (CAD) or design services engineer is responsible for delivering efficient, robust and high-quality design flow solutions. The design flow on a day-to-day basis keeps chip designers and verification engineers productive and focused on their jobs, preventing them from debugging CAD tools and flows and creating ad hoc and undocumented scripts. Over the life of a project, a high-quality design flow differentiates a company from competitors and can be the difference between getting chips to market first or being the victim of unexpected process bottleneck and delays.
And yet, every semiconductor project group deals with inefficiencies that constrain them from delivering ideal solutions and limits productivity. Today’s CAD engineers use a patchwork of tools, flows and scripts consisting of commercial electronic design automation (EDA) products, commercial or in-house customized add-ons and in-house intellectual property (IP), a problem for many project groups because of:
- Tool flow gaps in existing EDA products
- The burden of maintaining in-house or homegrown tools, flows and scripts
- The lack of time to build and test high-quality, robust internal tools
That inevitably leads to a bunch of problems, as explained in the following sections.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Articles
- EDA in the Cloud Will be Key to Rapid Innovative SoC Design
- Vital Ways to Prevent a Cyberattack
- Agile Analog's Approach to Analog IP Design and Quality --- Why "Silicon Proven" is NOT What You Think
- How to manage changing IP in an evolving SoC design
Latest Articles
- Terracotta: Enabling the Adoption of New DRAM Techniques via a Flexible DRAM Interface and Memory Controller
- A Framework for Accelerating Transformer Inference on RISC-V for Edge AI
- An Interleaved Parallel Dependent Quantization Hardware Architecture for H.266/VVC
- A Formal Security Analysis of CAN XL
- A Secure dToF LiDAR SoC with Dual-Domain Fingerprinting and Event-Driven AFE Circuit Achieving Sensor-Level Attack Resilience