Why Focus Solely on CPU & GPU When Reducing SoC Power?
Interconnect clock gating cuts SoC energy consumption
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated.
Most efforts to control power consumption in System-on-Chip design are focused on the computational units, such as the CPU and GPU. However, other sections of the chip remain largely untapped for energy conservation measures. SoC designers may put themselves at a market disadvantage if they miss the opportunity to reap game-changing power savings from design measures that may cut overall power by as much as 10%.
The SoC interconnect is one area in which efforts to reduce power consumption need be re-evaluated. In computational units such as the GPU or CPU, clock-gating is one of several measures commonly applied to reduce power consumption, but in other areas of the chip, this may have been overlooked.
To read the full article, click here
Related Semiconductor IP
- FlexGen Smart Network-on-Chip (NoC) IP
- FlexWay Interconnect IP
- Magillem Registers
- Magillem Packaging
- Magillem Connectivity
Related Blogs
- Why You Need to Consider Energy Efficiency of Your HPC SoC Early On
- Power, Not Area: Why Edge GPU Design Is Entering a New Era
- Balancing GPU workloads on PowerVR hardware
- Scaling up vs scaling down. The real scoop on power-efficient GPUs for laptops
Latest Blogs
- World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
- One Key for Every Door: How Aliro Extends the UWB Digital Key Beyond the Car
- Reprogrammable Post-Quantum Security for SoCs: Why Crypto-Agility Matters
- Designing the Beam Steering Core for a C-Band AESA: A Look at VSI's VBF0644 GaAs Beamformer IC
- Secure Boot for embedded systems: Building a complete chain of trust