Visualizing Better Protocol Debug
The many wheels of technology, as much as we'd like them to, don't move ahead in lockstep fashion. Sometimes the demands of one technology outrun the benefits of an enabling technology.
Take debug: It’s a time sink. It consumes half the overall verification effort. On average, it takes engineers three to five cycles through the debug loop to isolate and fix a single bug. A big reason for the increase in debug time seen during the past decade is that designs have gotten significantly more complex, involving sophisticated object-oriented programming-based test benches, third-party IP, and embedded software running on many cores.
You’d think that as design complexity has increased that debug, as a supporting technology, would have advanced in parallel to meet the evolving challenges. But this isn’t the case. In fact many engineers are today using the same traditional debug process that’s been in place for 20 years: code, simulate, analyze some waveforms, debug. Repeat. Repeat. Repeat however many times it takes.
To read the full article, click here
Related Semiconductor IP
- Highly scalable performance for classic and generative on-device and edge AI solutions
- MIPI CSI-2 TX Controller
- 1.6T Ultra Ethernet Controller
- HBM4E PHY and controller
- HBM3 PHY
Related Blogs
- Overcoming the Protocol Debug Challenge
- Case Study: How To Use Protocol Debug Analyzer To Simplify Debug
- Protocol Debug for Complex SoCs
- Reduce Protocol Debug Time with Memory VIP
Latest Blogs
- IDS-NoC: A Scalable Interconnect Solution for Modern SoC Design
- Leading-edge AI IC designs demand comprehensive HAV methodologies
- Beyond the Fab: Building Europe’s Next Generation of Semiconductor Champions
- AI Semiconductor Design at 3nm and 2nm: Silicon-Proven IP
- Samsung Foundry and Cadence Expand Infrastructure and Physical AI Solution