Visualizing Better Protocol Debug
The many wheels of technology, as much as we'd like them to, don't move ahead in lockstep fashion. Sometimes the demands of one technology outrun the benefits of an enabling technology.
Take debug: It’s a time sink. It consumes half the overall verification effort. On average, it takes engineers three to five cycles through the debug loop to isolate and fix a single bug. A big reason for the increase in debug time seen during the past decade is that designs have gotten significantly more complex, involving sophisticated object-oriented programming-based test benches, third-party IP, and embedded software running on many cores.
You’d think that as design complexity has increased that debug, as a supporting technology, would have advanced in parallel to meet the evolving challenges. But this isn’t the case. In fact many engineers are today using the same traditional debug process that’s been in place for 20 years: code, simulate, analyze some waveforms, debug. Repeat. Repeat. Repeat however many times it takes.
To read the full article, click here
Related Blogs
- Overcoming the Protocol Debug Challenge
- Case Study: How To Use Protocol Debug Analyzer To Simplify Debug
- Protocol Debug for Complex SoCs
- Reduce Protocol Debug Time with Memory VIP
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era