A standard who's time must come - SCE-MI
A few days ago Toshio Nakama, CEO of S2C wrote a blog titled “Why SCE-MI has not been Widely Adopted Today?” First of all, hands up if you know what SCE-MI is. Not a lot of hands up. OK, hands up if your company uses emulation or FPGA prototyping. Lot more hands up now. Well, you are probably a user of SCE-MI. It is the standard that defines how hardware assisted platforms talk to software - that a testbench, software simulator or virtual prototype.
To read the full article, click here
Related Semiconductor IP
- TSMC 7nm 0V75 / 0V9 ESD Local Clamp – Low Cap
- TSMC 65nm 3V3 ESD Local Clamp – Rad Hard
- TSMC 5nm 1V8, 1.2V and 0.9V ESD Local Protection – Low Cap
- TSMC 3nm 3V3 ESD Local Clamp
- TSMC 3nm 1V2 ESD Local Clamp – Low Capacitance
Related Blogs
- Do we need a new FPGA structure for prototyping?
- Virtual Platforms plus FPGA Prototyping, the Perfect Mix
- FPGA Prototyping of System-on-Chip (SoC) Designs
- FPGA Prototyping: From Homebrew to Integrated Solutions
Latest Blogs
- Beyond Trusted: What the NSA’s New Guidance Means for Hardware Security
- A scalable, shader-programmable vector graphics GPU core for low-power MCUs
- Navigating ISO 26262 Part 11: A Guide for Semiconductor Architects
- Embedded Security explained: Digital signatures
- Hardware security verification must go beyond functional testing