Neural Networks and the Future
The recent embedded neural network symposium held at Cadence wrapped up with a panel session. Chris Rowen was the moderator and I think the panelists were Han Song, Ren Wu, Forest Iandola, Kai Yu and Jeff Bier (who all presented earlier). I didn't really note down who said what so I'll just report on some of the points that were made. Stuff in [square brackets] are my additional comments, not something any of the panelists said explicitly.
During the sessions, several speakers talked about how 8 bits (or even 4 bits or, in some cases, 2) are precise enough, and 32-bit floating point isn't really needed. But all of the real-world applications seem to be sticking with GPUs. The panelists figured that it was the lack of experience, it is only just showing up in the literature now. Everyone is excited by how fast the field is moving but the approaches actually being deployed are changing much more slowly. It only takes one highly visible success to move people, but going from 0 to 1 is really hard.
To read the full article, click here
Related Semiconductor IP
- Highly scalable performance for classic and generative on-device and edge AI solutions
- MIPI CSI-2 TX Controller
- 1.6T Ultra Ethernet Controller
- HBM4E PHY and controller
- DDR5 MRDIMM PHY and Controller
Related Blogs
- eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
- ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
- On-chip networks: Future of SoC design
- Embedded Vision: The Road Ahead for Neural Networks and Five Likely Surprises
Latest Blogs
- From AI-Assisted EDA to AI-Mediated Engineering
- Simplifying Multi-Domain Voltage-Control Verification with Synopsys AVSBus 2.0 VIP
- The Cyber Resilience Act Is Turning Hardware Security into an Evidence Question
- Inside the Arm Mali G2-Ultra NX GPU: Delivering desktop-class mobile gameplay with AI-native graphics
- Synopsys Joins Arm Total Design for Physical AI to Advance Autonomous Systems