Vendor: Cadence Design Systems, Inc. Category: DDR

DDR5 MRDIMM PHY and Controller

Leading-edge IP for high-performance multi-channel memory systems

Controller + PHY DDR5 View all specifications

Overview

The industry-first Cadence DDR5 12.8Gbps MRDIMM Gen2 PHY and controller memory IP system solutions double the performance of DDR5 DRAM. The DDDR5 12.8Gbps design and architecture address the need for greater memory bandwidth to accommodate unprecedented AI processing demands in enterprise and data center applications, including AI in the cloud.

The DDR5 MRDIMM Gen2 IP system solution is available today, ready to enable advanced SoCs with flexible floorplan design options, while at the same time, the architecture allows fine-tuning of power and performance based on individual application requirements.

Cadence supports your SoC/IP integration and development with EDA tools, Verification IP (VIP), and Rapid System Bring-Up software.

Key features

PHY

  • Includes DDR5 training with write-leveling and data-eye training, and I/O pads with impedance calibration logic and data retention capability
  • Programmable per-bit (PVT compensated) deskew on read and write data paths
  • RX and TX equalization for heavily loaded systems
  • Microcontroller-based PHY-independent advanced training that provides flexibility
  • Low latency for data-intensive applications
  • Signal integrity, board, and package design guidelines

Controller

  • QoS features allow command prioritization on Arm AMBA 4 AXI and CHI interfaces
  • Memory controller interface complies with DFI standards up to version 5.1

Block Diagram

DDR5 MRDIMM PHY and Controller block diagram

Benefits

  • Scalable: The flexible floorplan design options enable easy integration into advanced SoCs, allowing for scalable solutions that can grow with your needs.
  • High Performance: Industry-first Cadence DDR5 12.8Gbps MRDIMM Gen2 PHY and controller doubles the performance of DDR5 DRAM.
  • Enhanced Memory Bandwidth: Addresses the need to accommodate AI processing demands in enterprise and data center applications.
  • Power and Performance Tuning: The architecture allows fine-tuning of power and performance based on individual application requirements.

Specifications

Identity

Part Number
DDR5 MRDIMM PHY and Controller
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY

Standards & Interfaces

Memory
DDR5

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about DDR IP core

DFI 6.0 Key Highlights of the Latest DFI Specification

DFI 6.0.1 (also referred to as DFI 6.0 in the rest of the blog) is the latest standard of the DFI specification. It removes support for earlier DDR/LPDDR generations, adds support for LPDDR6 and HBM4, adds/modifies low-power features, reorganizes WCK and memory-error handling, removes the disconnect protocol, and adds support for 1:3 and 1:6 DFI ratios.

SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the data center as an alternative to external CPU memory, due to its high performance, low power, memory capacity, and scalability.

Heterogeneous Multicore using Cadence IP

This blog presents a heterogeneous multicore system built with the RISC-V Host CPU and Cadence IP: Xtensa DSPs, and the Janus Network-on-Chip (NoC). While this example uses an RISC-V CPU, any other ISA with similar capabilities can also serve as the host CPU.

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes and cautionary failures. The difference often hinges on when problems are discovered. A bug found late in development can derail timelines and budgets. This is why "shifting left"—moving testing and validation earlier in the process—is now a critical strategy for innovation.

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter path forward. Cadence's blog, "Boosting AI Performance with CXL," outlines how CXL enables dynamic memory expansion, memory sharing, and maintains coherency across devices to eliminate bottlenecks and boost performance for processing training and inference in large-scale AI systems.

Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

Cadence continues to invest significant engineering effort to deliver advanced, user-friendly IP solutions across a range of essential protocols, two of which were on display at the recent Future of Memory and Storage (FMS) conference in Santa Clara, CA.

Frequently asked questions about DDR Interface IP

What is DDR5 MRDIMM PHY and Controller?

DDR5 MRDIMM PHY and Controller is a DDR IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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