Memory Controller IP, battle field where Cadence and Synopsys are really fighting face to face. Today let's have a look at Cadence’s strategy
I have shared with you last year some strategic information released by Cadence in April about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.
To read the full article, click here
Related Semiconductor IP
- NPU IP
- JPEG XL Encoder
- I2C Master/Slave Controller Core
- NVMe Validation Test Suite
- Hybrid Memory Cube Verification IP
Related Blogs
- Controller Memory Buffer (CMB): NVMe 2.0’s On-Controller Memory Feature
- Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available
- Buying DDRn Controller IP AND Memory Model to the same IP vendor gives real TTM advantage
- How Secure DDR Interfaces Protect DRAM from Memory Attacks
Latest Blogs
- Tape-Out Readiness Checklist: Engineering Decisions That Prevent Costly Respins
- How Cadence DSPs Put In-Cabin AI Audio On-Chip in SemiDrive's X10
- The Fastest Path to Scalable Photonic Systems: Using Proven IP for both PIC and EIC designs
- Building Trusted AI Agents from the Silicon Root of Trust
- Heterogeneous Computing in Space