The interface makes the FPGA
November 26, 2009
Announcements from the FPGA industry this week continue the trend of the past year of placing the serial interface before the gate count or the core-logic IP – an understandable strategy, given the number of vertical markets for which interface virtually defines application (note that I did not say raw speed, though that is a secondary consideration).
Related Semiconductor IP
- Memory Simulation & Verification Platform
- PQC HW/SW IP Core
- PQC Co-Proc IP Core
- Poly IP Core
- Keccak IP Core
Related Blogs
- On-chip interfaces gain importance in next-gen FPGAs
- Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
Latest Blogs
- Secure Boot for embedded systems: Building a complete chain of trust
- Understanding PCIe 6.0 Power States: L0p vs L0s vs L1
- Crypto mining SoC unearths a need for custom IP
- Moving to AMBA® 5? Your AMBA® 4 IP Can Still Come With You
- Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now