On-chip interfaces gain importance in next-gen FPGAs
August 12, 2013
Maybe it was mere coincidence that Altera Corp announced new work with Cavium on multiprocessing, just as the MemCon memory bus conference opened in Santa Clara. Maybe the new IP core pacts announced by Cadence, Synopsys, and Lattice were a tangential sideshow to MemCon. Or maybe there is a common realization that the future belongs to successful synthesizable implementations of DDR3, RDRAM, Interlaken, and other high-speed interfaces that operate intra-chip and inter-chip.
To read the full article, click here
Related Semiconductor IP
- Interlaken Verification IP
- Interlaken Intel® FPGA IP
- Interlaken Look-Aside Intel® FPGA IP
- Interlaken Verification IP
- Interlaken Synthesizable Transactor
Related Blogs
- The interface makes the FPGA
- SSD Interfaces and Performance Effects
- Altera's intros 28nm Stratix V FPGA family
- Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing
Latest Blogs
- Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A
- From Classical CAN and CAN FD to CAN XL: Functional Safety and Security for Next-Generation In-Vehicle Communication
- Accelerating Embedded Memory Performance with 16-bit xSPI PSRAM IP
- Why nonce reuse can break AES-GCM security in embedded systems
- PQSecure™-Agility Earns NIST CAVP Validation