Cadence Leads the Pack: The First VIP for USB4 is Here!
On March 14th, Cadence announced the release of the industry’s first USB4-supporting Verification IP! The Cadence VIP for USB4 allows engineers to design and create cutting-edge SoC designs compliant with the current standards that are completely functionally verified and require less time.
“Support from [USB Implementers Forum] members like Cadence helps reduce the barriers to adoption of new USB protocols and enables innovative products from new industries to enter the market,” says Jeff Ravencraft, USB-IF President and COO.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs
- VESA Adaptive-Sync V2 Operation in DisplayPort VIP
- Validating UPLI Protocol Across Topologies with Cadence UALink VIP
- Understanding USB4 Retimers and Their Role in Gen2 and Gen3 - Link Training
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU