Accreditation Without Compromise: Making eFPGA Assurable for Decades
March 10, 2026
Expert Perspectives on Semiconductor IP and SoC Design Archive - Page 8 of 196
Synopsys Delivers First Complete UFS 5.0 and M‑PHY v6.0 IP Solution for Next‑Gen Storage
March 10, 2026
World First: Synopsys MACsec IP Receives ISO/PAS 8800 Certification for Automotive and Physical AI Security
March 10, 2026
Last-level cache has become a critical SoC design element
March 9, 2026
From driveway to checkout: seamless indoor navigation powered by UWB
March 9, 2026
Serial Wire Debug (SWD) Protocol: Efficient Debug Interface for Arm-Based System
March 6, 2026
ChiPy®: Bridge Neural Networks and C++ on Silicon — Full Inference Pipelines with Zero CPU Round-Trips
March 6, 2026
Securing RISC-V Third-Party IP: Enabling Comprehensive CWE-Based Assurance Across the Design Supply Chain
March 4, 2026
Power, Not Area: Why Edge GPU Design Is Entering a New Era
March 4, 2026
The On-Device LLM Revolution: Why 3B-30B Models Are Moving to the Edge
March 4, 2026
A CHERI on Top: A Better Way to Build Embedded Secure SoCs
March 3, 2026
How 224G SerDes Unifies Today’s AI Fabrics
March 2, 2026
Silicon Insurance: Why eFPGA is Cheaper Than a Respin
February 28, 2026
One Bit Error is Not Like Another: Understanding Failure Mechanisms in NVM
February 26, 2026
Introducing CoreCollective for the next era of open collaboration for the Arm software ecosystem
February 25, 2026
Integrating eFPGA for Hybrid Signal Processing Architectures
February 25, 2026
eUSB2V2: Trends and Innovations Shaping the Future of Embedded Connectivity
February 25, 2026
Securing UALink: Introducing Synopsys UALinkSec_200 Security Module
February 24, 2026
AI is stress-testing processor architectures and RISC-V fits the moment
February 19, 2026
Rambus Announces Industry-Leading Ultra Ethernet Security IP Solutions for AI and HPC
February 19, 2026
