Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

By Cadence

July 27, 2026

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital and custom design enablement, advanced packaging support, and power delivery-optimized flows for AI, HPC, mobile, and future aerospace applications.

Cadence's AI-driven digital and custom reference flows, tools, and solutions are now certified on Intel 18A-P and Intel 14A technologies, based on the latest Intel Foundry process design kits (PDKs). Building on the companies' recent expansion of design IP optimized for Intel 18A and 18A-P and their multi-year Design Technology Co-Optimization (DTCO) agreement targeting Intel 14A, this new certification provides customers with a signoff-ready path to deploy advanced AI, high performance computing (HPC), and mobile SoCs on Intel Foundry's leading-edge nodes.

Cadence has worked closely with Intel Foundry to co-optimize tools, flows, and methodologies that fully leverage the innovations in Intel 18A, Intel 18A-P, and Intel 14A, including RibbonFET gate-all-around transistors and advanced backside power delivery technologies such as PowerVia and PowerDirect. By tightly coupling process capabilities with Cadence's agentic AI-driven EDA portfolio and high-performance design IP, customers can achieve industry-leading power, performance, and area (PPA) while reducing design risk and time to market.

The new certifications reinforce Cadence's participation in the Intel Foundry Accelerator Ecosystem Alliance programs, where Cadence is a founding member focused on delivering interoperable, scalable chiplet solutions and robust design enablement for Intel's advanced nodes. Together, Cadence and Intel Foundry are working to ensure that customers across AI factories, data centers, and mobile have access to signoff-ready flows, IP, and packaging technologies that accelerate innovation.

"As designers look for new ways to differentiate their products in this exciting era of AI, Intel Foundry's collaboration with ecosystem partners such as Cadence will help our customers turn their most ambitious ideas into reality," said Shawn Han, SVP and GM, Foundry Services, Intel Corporation. "Through co-optimized, certified design flows and silicon-validated IP, we give our customers greater confidence that they can design on next-generation Intel Foundry technologies to achieve their specific power, performance, and efficiency targets."

The certified digital and custom reference flows span the full Cadence portfolio of AI-driven implementation, verification, and signoff solutions, including synthesis, place-and-route, timing and power signoff, physical verification, reliability verification, and analog/custom design. These flows are tuned to the PDKs for Intel 18A-P and Intel 14A, enabling design teams to quickly adopt Intel Foundry's advanced nodes with flows jointly validated for manufacturability, reliability, and yield.

As part of the collaboration, Cadence and Intel Foundry have also co-developed an advanced packaging reference design flow that supports Intel Foundry's Embedded Multi-die Interconnect Bridge (EMIB) and EMIB-T technologies. This workflow streamlines the integration of complex multi-chiplet architectures by eliminating data conversion steps, enabling concurrent design activities, and providing early thermal, signal integrity, and power integrity analysis across dies and packages.

In addition, Cadence and Intel Foundry have validated IP test chips in silicon on Intel 18A using Cadence interface and memory IP, demonstrating robust interoperability between Cadence IP, AI-driven flows, and Intel Foundry's power delivery optimized process technologies. This silicon validation enables IP choice for customers across the various nodes offered by Intel Foundry.

Featuring RibbonFET 2 and PowerDirect second-generation gate-all-around and backside power delivery technologies, Intel 14A is expected to deliver higher performance at the same power compared to Intel 18A, making it a compelling choice for next-generation AI accelerators, cloud and edge HPC, premium mobile applications, and over time, aerospace and government designs.

"The next era of AI, HPC, mobile, and advanced systems innovation will be defined by how quickly customers can move from bold architectural ideas to reliable silicon," said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. "Our expanded collaboration with Intel Foundry brings together Cadence's AI-driven EDA portfolio, robust co-optimized certified flows and platform, silicon-validated IP, and advanced packaging flows with Intel's advanced process technologies, giving design teams a trusted, signoff-ready path to achieve their power, performance, and time-to-market goals on Intel 18A-P and Intel 14A."

Cadence will showcase the certified Intel 18A-P and Intel 14A flows, DTCO methodologies, and advanced packaging solutions at the Design Automation Conference (DAC), with technical sessions and demos highlighting customer use cases across AI, HPC, and mobile markets.

Customers interested in early engagement on Intel 14A and advanced packaging projects are encouraged to contact their Cadence and Intel Foundry representatives.