Understanding PCIe 6.0 Power States: L0p vs L0s vs L1

By Mamta Rana

July 15, 2026

PCI Express has always focused on a single goal: maximizing performance while minimizing power. However, with PCIe 6.0, maintaining this balance has become far more challenging. With PAM4 signaling in PCIe 6.0, link power is no longer a secondary concern—it is now a first-order design constraint. The PHY consumes significantly more energy, and modern workloads generate traffic patterns characterized by bursts of multiple flits rather than continuous transfers. 

This is where PCIe 6.0 introduces a major shift in power-state strategy: the real battle is no longer between L0 and L1—it is between L0p, L0s, and L1. 

In this blog, we explore how these states differ, why PCIe 6.0 changes the rules, and which one matters most moving forward. 

Why Power States Matter More in PCIe 6.0 

PCIe 6.0 doubles bandwidth compared to PCIe 5.0. While PCIe 5.0 relies on NRZ signaling, PCIe 6.0 adopts PAM4, along with Forward Error Correction (FEC) and FLIT mode to achieve higher throughput. 

However, these advancements come at a cost: 

• Increased PHY power consumption 

• Higher equalization complexity 

• Greater idle-to-active power overhead 

In this environment, remaining in L0 (fully active) during idle gaps becomes inefficient. Yet, modern workloads, especially in accelerators, AI, and storage systems consist in frequent micro-idle periods. 

Therefore, PCIe 6.0 requires power states capable of responding within microseconds, without compromising throughput or latency. 

PCIe Link Power-State Landscape 

PCIe defines multiple link states within the LTSSM (Link Training and Status State Machine). The most relevant states for active and idle operation are: 

PCIe 6.0 introduces L0p because neither L0s nor L1 alone can effectively handle modern workload demands. 

L0s: The Legacy “Quick Idle” State 

L0s was introduced as a fast idle state for short inactivity periods. 

In L0s, the transmitter may stop sending symbols, the receiver stays partially ready, and the link is still logically active.

But Why Did L0s Work in Older Generations?  

Because in previous generations the PHY power was manageable, the traffic/data patterns were simpler, and the wake latency requirements were relaxed. L0s provided moderate savings without much complexity. But L0s turn out to be limited to PCIe 6.0. At PAM4 as the equalization must remain stable, the continuous readiness becomes expensive. So L0s does not reduce enough PHY power to justify its use. So, the PCIe 6.0, L0s becomes less effective.

How About L1?  

Let us understand L1 now. L1 is a deeper, low-power idle state. In L1, most of the link circuitry powers down, and the exit requires a more involved wake sequence. Though it’s beneficial in terms of significant power savings and is ideal for long idle durations, it has higher exit latency and can disrupt low-latency fabrics (e.g., CXL) 

The modern PCIe traffic which consists of burst transfer and micro-idle gap, If the link enters L1 too aggressively, the wake overhead will hurt performance and will cause the latency-sensitive traffic to suffer. So PCIe 6.0 needs something between L0 and L1. 

Hence L0p Was Introduced 

L0p (Low Power L0) is a new PCIe 6.0 link state designed to reduce power while keeping the link operational and responsive. 

It is best described as: “Active mode, but PHY-optimized.” L0p sits between: 

• L0 (full activity) 

• L1 (deep sleep) 

In L0p, the link remains logically active, some portions of the PHY can be powered down, lane width may be reduced dynamically, and the exit latency is near-zero compared to L1. This makes L0p ideal for short idle gaps. 

L0p vs L0s vs L1: Key Comparison 

One unique PCIE 6.0 capability is that L0p may support dynamic link width changing.  

L0p supports:

• x16 → x8 → x4 downsizing during idle gaps. 
• Maintaining at least one active lane 
• Restoring full width instantly when traffic returns 

This is a major step toward the power aware of PCIe fabrics. So, in PCIe 6.0 systems, the emerging hierarchy is that L0 for full traffic, L0p for burst idle gaps, L1 for extended inactivity, and L0s becomes increasingly irrelevant. 

PCIe 6.0 changed the power management equation. L0 is too expensive to stay in during idle gaps; L1 saves power but adds latency, and L0s is no longer sufficient for PAM4 PHY power. Hence L0p fills the critical missing middle.

L0p is not just another low-power state. As PCIe evolves toward Gen 6.0 and forward and on CXL fabrics, L0p will become foundational for more output for less power. 

Explore Cadence IP:

• Controller for PCIe
• Simulation VIP for PIPE PHY
• Simulation VIP for PCIe

 To learn more about Cadence solutions for PCIe and CXL verification, explore these resources: 

• VIP for PCI Express
• TripleCheck Test Suite

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website 

If you have more feedback or need more information, reach out to us at talk_to_vip_expert@cadence.com