The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
April 15, 2026
Expert Perspectives on Semiconductor IP and SoC Design Archive - Page 4 of 194
Considerations When Architecting Your Next SoC: NoCs with Arteris
April 14, 2026
Implementing Dual-core Lockstep in the CHIPS Alliance VeeR EL2 RISC-V core for safety-critical applications
April 14, 2026
Rethinking Display Safety: Why RISC-V-Supervised DisplayPort Subsystems Enable Secure, Isolated Automotive Architectures
April 14, 2026
Area, Pipelining, Integration: A Comparison of SHA-2 and SHA-3 for embedded Systems.
April 9, 2026
Why Your Next Smartphone Needs Micro-Cooling
April 9, 2026
Teaching AI Agents to Speak Hardware
April 9, 2026
SOCAMM: Modernizing Data Center Memory with LPDDR6/5X
April 9, 2026
Bridging the Gap: Why eFPGA Integration is a Managed Reality, Not a Schedule Risk
April 9, 2026
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
April 8, 2026
The Architectural Evolution of 16GHz PLLs for Next-Gen AI and SerDes SoCs
April 7, 2026
On-Device AI Semiconductors & High-speed Interconnects in the Physical AI era
April 7, 2026
Google, Quantum Attacks, and ECDSA: Why There’s No Need to Panic and Why Preparation Matters Now
April 6, 2026
One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation
April 6, 2026
What is the EDA problem worth solving with AI?
April 2, 2026
Synopsys Advances Die‑to‑Die Connectivity with 64G UCIe IP Tape‑Out
April 2, 2026
The 5 Biggest Challenges in Modern SoC Design (And How to Solve Them)
April 1, 2026
Can Your NPU Run DOOM? Chimera Can.
March 31, 2026
Importance Of Hardware Security Verification In Pre-Silicon Design
March 30, 2026
Arteris × XuanTie: The “Data Highway” for High-Performance RISC-V SoCs
March 30, 2026