Moving to AMBA® 5? Your AMBA® 4 IP Can Still Come With You

By CAST, Inc.

July 14, 2026

As SoC architectures adopt AMBA^® 5 fabrics and components, many proven IP blocks still rely on AMBA^® 4 or earlier interfaces. That creates a common integration problem: how do designers connect newer AMBA^® 5 system components to existing IP without redesigning the IP or replacing verified blocks?

For many SoC teams, the answer is not a full interface rewrite. It is a bridge.

The Integration Challenge

AMBA^®-based SoCs often contain a mix of interface generations. Newer infrastructure may use APB5, AXI5, or AXI5-Stream, while existing IP blocks may still expose APB3/APB4, AXI4, AXI4-Lite, or AXI4-Stream interfaces.

That matters because many control and status register interfaces are implemented with APB3/APB4 or AXI4-Lite. High-throughput data-path IP, including compression cores, hardware protocol stacks, TSN cores, and other peripherals, often uses AXI4-Stream.

Without a bridge, integrating these blocks into an AMBA^® 5 environment may require additional wrapper logic, interface modification, or IP-level changes. That adds engineering effort and can increase verification scope.

Bridging AMBA^® 4 IP into AMBA^® 5 Systems

CAST’s new AMBA^® bridge cores are designed to support backward compatibility and IP reuse in mixed-generation SoCs. They allow existing AMBA^® 4-based IP to communicate with newer AMBA^® 5 components and fabrics while preserving the original IP interface.

The bridge family includes three cores:

APB-BRG: APB5 to APB4 Bridge

APB-BRG connects an APB5 interface to IP blocks with APB4 or earlier register-access interfaces. This is useful for control and status register access across many existing peripheral and subsystem cores.

The core handles APB5-related additions including wakeup signaling, user signaling, PNSE extension, parity checking, and configurable error handling. It also supports configurable address, data, and user signal widths.

AXI-BRG: AXI4 to/from AXI5 Bridge

AXI-BRG enables communication between AXI4 and AXI5 manager/subordinate interfaces. It can be used with both AXI4 master and slave interfaces, including those found in DMA cores, TCP/IP hardware stacks, and other system-level IP.

The core supports full AXI and AXI-Lite modes, making it useful for both data movement and control/register interfaces. It implements key AMBA^® 5 interface features including wakeup signaling, poison signaling, parity checking, configurable bus widths, and configurable error handling.

AXIS-BRG: AXI4-Stream to/from AXI5-Stream Bridge

AXIS-BRG bridges AXI4-Stream and AXI5-Stream interfaces in either direction. This is useful for streaming-data IP such as compression engines, hardware stacks, TSN cores, and other peripherals that move data through AXI4-Stream channels.

The core handles AXI5-Stream additions including TWAKEUP and parity check signals. It also supports configurable data and user widths, allowing it to be adapted to different streaming datapaths.

Preserving IP Investment While Updating the SoC

The value of these bridge cores is straightforward: they help engineering teams keep using proven AMBA^® 4 IP inside newer AMBA^® 5 systems.

Instead of modifying verified IP blocks, designers can place a bridge at the interface boundary. That reduces integration effort, limits design disruption, and helps preserve existing verification investment. For SoCs that combine newer AMBA^® 5 fabrics with established APB4, AXI4, AXI4-Lite, or AXI4-Stream IP, these bridges provide a practical migration path.

CAST’s APB-BRG, AXI-BRG, and AXIS-BRG cores give SoC teams a clean way to modernize system connectivity without leaving existing IP behind.