Tardigrade, an ASIC synthesis engine designed for AI

By Andreas Olofsson

July 10, 2026

Zero ASIC, a U.S. semiconductor startup on a mission to democratize silicon, today announced the release of Tardigrade^™, a state of the art ASIC synthesis engine designed for the age of AI driven chip design.

Background

When DARPA kicked off the IDEA and POSH programs in 2017¹ to build “No Human In the Loop” chip compilers, machine learning for chip design was still very much in a nascent state and I don’t recall even the most optimistic person predicting anything close to what we are experiencing with today’s state of the art LLMs. While the IDEA and POSH R&D programs produced some of the earliest indicators that fully automated analog, PCB, and system design by intent is actually possible, it was still essentially research. (Paper!=product.) For example, the OpenROAD project which was launched as part of the DARPA IDEA program in 2017 is still chipping away at feature completeness. This is not a knock on the OpenROAD team or technology (which are both awesome!), but an indication of how incredibly complex chip design has become. For the record, Zero ASIC has been using OpenROAD in our design flow since 2022, and while we still use commercial EDA tools for tapeouts at advanced nodes, OpenROAD has become an indispensable tool for automated architecture exploration, design planning, and virtual prototyping.²

Unless you have been asleep at the wheel for the last year, you would have noticed that the chip design and verification capabilities of LLMs (like Claude) are advancing at an incredible pace and can today be considered production grade. The question isn’t IF but HOW you apply LLMs in your chip design and verification tasks. From my own recent LLM experiences, it has become clear that to unlock the next level of productivity gains in LLMs, we again need to double down on the “No Human In the Loop” call to action that DARPA signaled in 2017!

Incrementally prompting can be a valid exploration process, but humans can only think and act so fast. To unlock the next 10-100X in chip design productivity, we need to get the human reviewer out of the loop and integrate ground truth validation into a closed loop system. Given the ubiquitous access to subscription/token based LLMs and near limitless cloud resources, it seems obvious that we need chip design validation tools that can scale 1 to 1 with those limitless computing resources.

In the domain of logic synthesis, an obvious solution would be to bring existing open source tools (abc, yosys)³ into the LLM agent loop, but the QoR simply isn’t good enough to make that practical today. A complex CPU core that easily reaches 1GHz in commercial EDA synthesis tools would only reach 200MHz using existing open source tools. A 5X frequency gap is too large a performance gap to make existing open source tools useful for advanced chip design.

The Tardigrade Solution

Closing the existing QoR performance gap in open chip compilers is NOT impossible (after all there are 3+ commercial EDA companies who have cracked the synthesis problem!), but it does require experts with a very specific set of skills to pull it off. Thankfully I was able to convince one of those experts, Dr. Thierry Besson, to join us at Zero ASIC last year.

Over the last 12 months, Thierry has single-handedly developed two state-of-the-art synthesis engines: the open-source Wildebeest for FPGA designers and Tardigrade for ASIC designers.

Developed from scratch to support the massive parallel scale required by autonomous AI agents, Tardigrade delivers commercial-grade quality without the legacy friction:

• Built for AI Workflows: Native, standardized QoR JSON metrics for easy LLM parsing, ultra-fast incremental timing optimization loops, and cloud-scale infrastructure integration via SiliconCompiler.
• Unbounded Scale: Zero license token limits, allowing AI agents to spin up thousands of synthesis runs simultaneously in the cloud.
• Silicon-Ready Performance: 1 GHz+ clock frequency timing closure, advanced node technology mapping, and full SDC timing-driven optimization support.
• Massive Capacity: Production-ready elaboration for synthesizable SystemVerilog handling designs larger than 5 million instances.

Benchmark Results

While industry NDA restrictions prevent us from publishing direct side-by-side comparisons with proprietary commercial tools, the performance leap over current open-source alternatives is profound. The following table illustrates timing improvements provided by Tardigrade on a set of representative circuits from the LogikBench RTL benchmark suite:

Access Model

Tardigrade has already been used successfully by the internal Zero ASIC design team and while Tardigrade will never be a traditional commercial EDA product, Zero ASIC is open to discussing partnerships and source code access.

About Zero ASIC

Zero ASIC is a semiconductor startup based in Cambridge, Massachusetts. The company mission is to democratize access to silicon through chiplets and design automation. Zero ASIC is building the world’s first composable chiplet platform, enabling billions of unique silicon systems to be assembled in hours from a catalog of off-the-shelf chiplets.

References

1. A. Olofsson, Intelligent design of electronic assets (idea) & posh open source hardware (posh), DARPA BAA, Sept, 2017 

2. A. Olofsson, et al, “A distributed approach to silicon compilation”, DAC, 2022 

3. R. Brayton and A. Mishchenko, “ABC: An academic industrial-strength verification tool”, Proc. CAV 2010 

4. Run via the stock SiliconCompiler Yosys flow using the LambdaPDK asap7 PDK and verified using the OpenSTA timing engine. All optimization and timing analysis is run in the slow (SS) corner. 

5. Run via Tardigrade using the LambdaPDK asap7 PDK and verified using the identical timing setup as in Note1.