65nm to 45nm SerDes IP Migration Success Story
May 27, 2011
The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.
The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).
After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.
To read the full article, click here
Related Semiconductor IP
Related Blogs
- Rambus LPDDR5T/5X/5 Controller IP Turbocharges AI Inference Performance to 9.6 Gbps
- Synopsys Secures Connected Vehicles with Industry's First IP Product to Achieve Third-Party Certification for ISO/SAE 21434 Cybersecurity Standard
- Synopsys Introduces Industry's First 40G UCIe IP Solution to Power High-Performance Multi-Die Designs
- Migrating the CPU IP Development from MIPS to RISC-V Instruction Set Architecture
Latest Blogs
- Designing for What Comes Next in AI
- Secure boot on Efinix Titanium Ti60: Getting started with KiviBoot-Tiny
- How Long Does It Take to Port a New AI Model? Minutes Now, and Falling
- PCI Express Security and TEE Integration, Part 1 - Establishing Trust
- World Models at the Edge, in Real Time: V-JEPA 2.1 on the Quadric GPNPU