65nm to 45nm SerDes IP Migration Success Story
May 27, 2011
The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.
The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).
After the first migration, business opportunities arose requiring the same SerDes IP to be moved to two further different 40nm processes.
To read the full article, click here
Related Semiconductor IP
- MIL-STD-1553 Controller IP
- UFS 5.x Device IP
- UCIe 3.x Controller IP
- Ethernet 800G PCS IP
- CHI to UCIe Bridge IP
Related Blogs
- Process technology analysis: Navigating analog IP migration with precision
- World IP Day: A Time to Reflect on the Value of Semiconductor IP
- Rambus CXL IP: A Journey from Spec to Compliance
- Rambus LPDDR5T/5X/5 Controller IP Turbocharges AI Inference Performance to 9.6 Gbps
Latest Blogs
- CDM Dependence on Device Capacitance
- What the Cyber Resilience Act means for the future of chip design
- When Your IP Vendor Has Operated 150,000 Base Stations: Introducing Viettel Semiconductor
- Relationship between architecture and validation in system design
- The Post-Quantum Cryptography Mandate: Building Cryptographically Agile Systems for the Quantum Era