SPAUI IP Listing

Ceva-RealSpace is a Spatial Audio software solution combining precise 3D rendering and accurate, low-latency head tracking.

• Audio Analog

The Spatial image transformation core is a signal processing accelerator designed for single or multi-channel image manipulations…

• Image Conversion
• AXI-Stream, AXI4-Lite

This IP includes a recommendation-compliant 802.11ax PHY layer C floating-point code for the Station (STA) mode.

• Wi-Fi

Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.

• Edge AI Accelerator
• now

Revolutionary dataflow architecture optimized for AI workloads with spatial compute arrays, intelligent memory hierarchies, and r…

• Edge AI Accelerator

The H264-E-CFS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standar…

• Video Processing

Each nearbAI core is an ultra-low power neural processing unit (NPU) and comes with an optimizer / neural network compiler.

• Edge AI Accelerator
• Available now

ASICFPGA 2D+3D Noise Reduction Core: Noise reduction is a key issue in any camera system to improve the visual appearance of the …

• ISP Image Signal Processor

The LLEMAC-1G implements an Ethernet Media Access Controller (MAC) compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.…

• Ethernet

The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standar…

• Video Processing

The H264-E-BPS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standar…

• Video Processing

The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital proc…

• ISP Image Signal Processor

The xc-SDDIB is a low-cost deinterlacing IP core that converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 pr…

• Video Processing
• FPGA
• Now

The LIN-CTRL core is a communication controller that transmits and receives LIN frames to perform serial communication according …

• LIN

Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…

• MIPI

The Extensible Radio Access Network (O-RAN WG4 Fronthaul Interface) defines a fronthaul interface between a lower-layer split dis…

• Cellular

The Image Signal Processing (ISP)-- ISI700 receives camera sensor data via the 4-channel DVP interface.

• ISP Image Signal Processor

First to market with multiple early adopters of production designs.This Cadence® Verification IP (VIP) provides support for the H…

• Verification IP

In production since 2014 on dozens of production designs.This Cadence® Verification IP (VIP) supports the JEDEC® Memory Device DD…

• Verification IP

IEC61162 Verification IP provides an smart way to verify Maritime navigation and Radio Communication equipment and systems when i…

• Verification IP