Vendor: Xicore Category: Video Processing

Standard Definition Video (PAL/NTSC) De-Interlacer, Basic Algorithm

The xc-SDDIB is a low-cost deinterlacing IP core that converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 pr…

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Overview

The xc-SDDIB is a low-cost deinterlacing IP core that converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used either for display or further processing such as H.264 video compression. The core uses a spatial predictor and complex two-dimensional filter to optimally compute pixels on missing lines on a pixel by pixel basis. This combined approach produces the highest possible quality for non motion-adpative deinterlacing.

Key features

  • Deinterlaces standard 4:2:2 interlaced video streams into 4:2:0 raster streams.
  • Spatial predictor and two-dimensional interpolation filter produces very high image quality.
  • Directly connects to 8-bit, 4:2:2 interlaced video source
  • Video format support includes either BT.656 or raw input with HSYNC,VSYNC timing.
  • Extremely low input-output latency of two video lines.
  • Variable output frame rate starting with twice the input field rate (50 fps)
  • Configurable input truncator supports D1, 4CIF and VGA sizes.
  • Very low core frequency equal to the output pixel rate (typically 27Mhz).
  • Simple external memory interface suitable with a wide variety of memory controllers
  • Fully synchronous, pipelined design
  • Bit-accurate executable model
  • Comprehensive testbench and documentation
  • Reference designs available

What’s Included?

  • Core netlist or RTL source code
  • Synthesis constraints
  • Comprehensive testbench with input video test file library, regression test scripts
  • Windows/Linux bit-accurate model
  • Developer's guide, specifications and system integration guide
  • Complete reference design (optional)

Specifications

Identity

Part Number
xc-SDDIB
Vendor
Xicore
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xicore
HQ: Israel
Contact Xicore

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is Standard Definition Video (PAL/NTSC) De-Interlacer, Basic Algorithm?

Standard Definition Video (PAL/NTSC) De-Interlacer, Basic Algorithm is a Video Processing IP core from Xicore listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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