Overview
ASICFPGA Advanced 2D+3D Noise Reduction Core: Noise reduction is a key issue in any camera system to improve the visual appearance of the images. As the light level decreases, the noise level increases to get appropriate brightness levels in the camera system. Our noise reduction core removes noises using Motion adaptive temporal noise filter and new advanced 2D noise filter. And our new noise reduction core can keep edge sharpness in spite of removing both color noise and luminance noise. At some noise level range, a 2D noise filter could remove noises. However, in some low lighting conditions, there is a limit to eliminating many temporal noises. With the performance improvement of new advanced 2D noise filter, the performance of 2D+3DNR filter is improved also. So ghost images are less than the previous versions of Core.
Our noise reduction core removes noises using Motion adaptive temporal noise filter and 2D spatial noise filter. In bright lighting conditions, 2D spatial noise filter can remove noises effectively because the noise level is low. In low light conditions, the gain of the sensor is increased, so the noise level is increased significantly. In this case, noises can be removed more effectively by using temporal noise filter than 2D spatial noise filter. Our core uses the motion adaptive temporal filter (MATF) for 3D temporal filtering. The MATF uses a motion detection instead of a motion estimator that is used for motion compensated temporal filter (MCTF). In general, the performance of MCTF has been known to be better than MATF. But the motion estimator in MCTF often produces the false motion vectors that can reduce the performance of the noise filter. And also the window size of motion estimation should be very large to guarantee the good filtering performance, so the logic size of the motion estimator becomes so big. Our core minimizes ghost images with using new advanced 2D noise filter
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