UHD Image Signal Processing (ISP) Pipeline

The logiISP-UHD Image Signal Processing Pipeline IP core is an Ultra High Definition (UHD) ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx ACAP, MPSoC, SoC and FPGA devices. It enables parallel processing of multiple Ultra HD video inputs in different programmable devices, ranging from the small Xilinx Artix®-7 FPGAs to the latest Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) devices. In comparison to simple instantiation of multiple ISP pipelines within a single programmable device, the latest IP cores’ improvements allow for tremendous savings of up to 50 % of valuable programmable logic.

The logiISP-UHD IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels, de-mosaics Bayer encoded video, makes image color and gamma corrections, filters the noise from the video, collects video analytics data for various control algorithms and manipulates video data formats and color domains. The IP core can be used with processor-based control algorithms for Auto White Balancing (AWB) and Auto Exposure (AE), which use video analytics data collected by the ISP pipeline. Xylon offers licensable AWB&AE libraries for the logiISP-UHD IP core.

The logiISP-UHD IP core supports spatial resolutions up to 7680x7680, including 4K2Kp60 (3840x2160@60fps) resolution, and accepts Raw Bayer, RGB and YCbCr video input formats featuring different pixel color depths (8/10/12-bit per pixel). It outputs RGB or YCbCr-formatted processed video and easily adapts to changing image sensor interfaces.

• Supports Xilinx® Versal™ ACAPs, Zynq® -7000 SoCs, Zynq UltraScale+™ MPSoCs, UltraScale™, UltraScale+ and 7-Series FPGA devices.
• Complete and configurable ISP pipeline includes:
  •  Raw Signal Processing (RSP):
    • Defective Pixel Correction
    • Spatial Noise Reduction
  • Color Filter Array Interpolation
  • Image Statistics (+ AWB & AE Support)
  • Color Correction Matrix
  • Gamma Corrections
  • Image Enhancement
  • Motion Adaptive Noise Reduction
  • YCbCr to RGB Color-Space Converter
  • RGB to YCbCr Color-Space Converter
  • Chroma Resampler.
• Digitally processes and enhances the quality of an input video stream and collects video statistics data for use in video control algorithms, i.e. Auto White Balance (AWB) and Auto Exposure (AE).
• High-Dynamic Range (HDR) operation mode is possible in combination with Xylon’s logiHDR IP core.
• Support for resolutions up to 7680x7680, including UHD 4K2Kp60 (3840x2160@60fps).
• Video input formats: Raw Bayer, RGB and YCbCr.
• Video input's bit width (pixel depth), depending on the type, can be as wide as 20-bit per component
• logiISP-UHD blocks that support 14/16/20-bit per component data inputs are as follows: RSP, CFA, STATS Pixel Picker, STATS Sum Of Color Values, STATS Quantum Luma Histogram, CCM and GAMMA
• Multiple channel video processing enables programmable logic savings: 1, 2, 3 or 4 input video channels.
• Video input and output are ARM® AMBA® AXI4-Stream protocol compliant.
• Optional registers are AMBA AXI4-Lite protocol compliant.
• Processing video blocks can be combined in different combinations and different processing orders.
  Parallel pixel processing with configurable number of pixels per clock: 1, 2 or 4.
• Parametrical VHDL design that allows tuning of slice consumption and features set.
• Prepackaged for Xilinx Vivado® Design Suite and fully controllable through the IP Integrator GUI interface.
• Evaluation IP core and bit-accurate C model available on request.
• IP deliverables include the software driver, documentation and technical support.
• Available fee-based license extension for AWB&AE libraries (logiISP-2A), which are verified with the logiISPUHD IP core.
   

• Application fields include Surveillance, Automotive Driver Assist, Machine Vision, Video Conferencing, Digital Signage, Medical Imaging, Aerospace and Defense, and others.