PLL - Input 8~24MHz, output 12~48MHz
IP
- PLL
- Mass Production
PLL - Input 8~24MHz, output 12~48MHz
IP
PLL - Input 4~27MHz, output 96~288MHz
IP
PLL - Input 4~24MHz, output 540~756MHz
IP
PLL - Input 27MHz, output 504~756MHz
IP
PLL IP, Input: 25MHz/50MHz/100MHz/125MHz, Output: 25MHz/125MHz/1.25GHz, UMC 0.13um HS/FSG process
high speed clock generator using UMC 0.13um 1.2V HS process.
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
40nm 1.1V 16MHz-2GHz Fractional-N Clock-PLL
The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm…
12-bit 12-Gsps Transceiver (ADC/DAC/PLL)
Unleash the power of precision and innovation with the NS_TRX_12G_T16, a 12-bit, 12-Gsps Transceiver with embedded ADC, DAC, PLL,…
General-purpose & Specialized Ring PLLs + RTL-based Solutions
Silicon Creations’ broad portfolio of general-purpose and optimized ring-based PLLs offer a wide range of clocking solutions.
MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
The MIPI D-PHY Analog TX IP Core adheres fully to version 1.2 of the D-PHY specification.
LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into ser…
VBO Transmitter with 8 lanes and 16 lanes for video communication
IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
MIPI M-PHY® 3.1 Analog Transceiver
MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
MIPI M-PHY® 4.1 Analog Transceiver
MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
MIPI C-PHY℠ v2.0 + D-PHY℠ v2.5 Combo IP Core
This Tx/Rx transceiver complies with the MIPI Alliance C-PHY℠ v2.0 and D-PHY℠ v2.5 specifications, with world-class area and powe…
The DP/eDP IP is designed for transmitting or receiving video and audio signals between the video source devices and display devi…
Power and Clock Generation IP - GLOBALFOUNDRIES® 22FDX®
Tightly integrated power management platform with a soft-IP wrapper around Analog / Mixed-Signal hard macros which generate all s…
Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…