Overview
The TRV301TSM40LP IP is a 1.1V low-power low-silicon-area 16MHz-to-2GHz Fractional-N Clock PLL implemented in TSMC Low-Power 40nm CMOS process technology. Its low loop filter bandwidth and low-frequency reference clock makes it especially suitable for use in clock synthesis for DAC, ADC and digital subsystems within wireless communication and broadcast integrated circuit chipsets (LTE, WiFi, WiMAX, DAB, DAB+, FM, HDFM, DRM, etc).
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Leveraging Tetrivis’ proven KuKa® transceiver IP—already sampling on a 40 nm node for customer demonstrations—the partners will translate the design to an advanced 12 nm process and package it as a UCIe-ready chiplet for next-generation satellite communications, phased-array radar, high-throughput backhaul and secure aerospace links.
Tetrivis LTD, a provider of specialist Analogue, Mixed-Signal, RF and mm-Wave Intellectual Property, has today taped out the TRV003 (Rx) and TRV004 (Tx) RF/mm- Wave Integrated Circuits for fabrication, the first chipsets in the KuKa™ family of Phased Array ASICs.