Tri-Mode Ethernet Media Access Controller (TEMAC)
The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications and storage equipment.
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Tri-Mode Ethernet Media Access Controller (TEMAC)
The TEMAC core is ideally suited for the development of high density Gigabit Ethernet communications and storage equipment.
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices.
SMIC 0.13um 1.2~3.3V Voltage Controlled Crystal Oscillator
This IP is a tunable continuous Voltage Controlled Crystal Oscillator (VCXO).
Aliathon’s 2.5Gbps GFP-F Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for …
Aliathon’s 2.5Gbps GFP-T Encoder Core provides a flexible, resource-efficient, high-density programmable logic based solution for…
Aliathons’s Multi-Channel E1/T1/J1 Framer Core provides a flexible, resource-efficient, high-density programmable logic based sol…
Aliathon’s HDLC Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for HDLC inte…
Aliathon’s ATM Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for ATM interf…
Aliathon’s Packet Over SONET/SDH (POS) Framer Core provides a flexible, resource-efficient, high-density programmable logic based…
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system …
Interleaving is a technique commonly used in communication systems to overcome correlated channel noise such as burst error or fa…
The Lattice SGMII and Gb Ethernet PCS IP core implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX…
Peripheral Component Interconnect (PCI) is a widely accepted bus standard that is used in many applications including telecommuni…
The Helion Modular Exponentiation core performs the Z = YE mod M computation which is at the heart of many commonly used Public-K…
VeriSilicon SMIC 0.15um LV High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corpora…
The Zaltys High Data Rate Demodulator (HDRM-D) and the Zaltys Enhanced High Data Rate Demodulator (HDRM-D2) IP cores efficiently …
LIN Bus Master/Slave Controller
The LIN-CTRL core is a communication controller that transmits and receives LIN frames to perform serial communication according …
USB 2.0 Host/Device Transceiver With On-The-Go (OTG)
USB 2.0 HOST/DEVICE/OTG Transceiver is a fully integrated PHY Core which is a super-set of HOST and DEVICE PHY with High Speed (H…
The USB 2.0 embedded host controller is designed for flexibility and ease of use; is available with a Software stack; facilitates…