Vendor: VeriSilicon Microelectronics (Shanghai) Co., Ltd. Category: SRAM

SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler

VeriSilicon SMIC 0.15um LV High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corpora…

SMIC 150nm LV Silicon Proven View all specifications

Overview

VeriSilicon SMIC 0.15um LV High-Speed Synchronous Memory Compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.15um Logic Low Voltage 1P7M Salicide 1.2/3.3V process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of words and bits. While satisfying speed and power requirements, it was optimized for area efficiency.
VeriSilicon SMIC Synchronous Memory compiler uses four layers within the blocks and supports metal 4, 5, 6 or 7 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.

Key features

  • 1.2v Low Voltage power supply
  • High Density
  • High Speed
  • Size Sensitive Self-Time Delay for Fast Access
  • Automatic Power Down
  • Tri-State Output(SRAM only)
  • Write Mask Function(SRAM & Register File)
  • More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/WorldwideOffice.html

Silicon Options

Foundry Node Process Maturity
SMIC 150nm LV Silicon Proven

Specifications

Identity

Part Number
SMIC15LV_MC
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP

Provider

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler?

SMIC 0.15umLV Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Silicon Proven.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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