ATM Framer
Aliathon’s ATM Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for ATM interf…
Overview
Aliathon’s ATM Framer Core provides a flexible, resource-efficient, high-density programmable logic based solution for ATM interfacing. Running at 155MHz, it is capable of processing thousands of ATM channels.
Key features
- Conforms to ITU I.432.1.
- Best-in-Class size and performance. Supports many thousands of channels.
- Multiple FPGA vendor support.
- Processes data for multiple independent TDM ATM streams.
- Configurable IDLE and Unassigned Cell insertion, detection and deletion.
- Optional HEC insertion; HEC error detection and correction.
- Supports multiple stream processing for glueless interfacing in multi-channel PDH systems.
- Supports dynamically ranged streams between 1 and 8 bits wide.
- Byte wide interface allows easy interface to Aliathon’s OC3/STM1, OC12/STM4 and 2xOC12/STM4 channelized systems.
- Configuration may be applied to each stream independently, and changed dynamically.
- Full Overhead and Defect processing per channel including:
- LCD, Uncorrectable HEC, Correctable HEC, Good HEC, IDLE detected.
- Performance Monitoring counters (Uncorrectable HEC, Correctable HEC, Good HEC).
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about TDM Framer IP cores
What is ATM Framer?
ATM Framer is a TDM Framer IP core from Aliathon Ltd listed on Semi IP Hub.
How should engineers evaluate this TDM Framer?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this TDM Framer IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.