Smart Card Reader Controller
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system …
Overview
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces.
The SCR supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications, which define the electrical signals and transmission protocols for smart cards (also known as integrated circuit cards). It acts as a communication controller, passing data to and from the host system and the smart card. It is fully-featured, and can activate and deactivate cards, perform cold/warm resets, handle ATR response reception, and execute other essential functions.
The SCR consists of the core smart card reader logic with a wrapper for the desired system interface. (AMBA APB interface is available; support for AMBA AXI4-Lite, Avalon-MM or Wishbone is optional.)
The core is fully synchronous for easier testing and is designed for efficient ASIC or FPGA implementation. It requires, for example, just 6,500 ASIC gates and operates at 300 MHz (TSMC 0.13). This smart card reader core has been rigorously verified and multiple times production-proven.
Key features
- Supports the ISO/IEC 7816-3:2006 and EMV 4.3 specifications
- Performs functions needed for complete smart card sessions, including:
- Card activation and deactivation
- Cold/warm reset
- Answer to Reset (ATR) response reception
- Data transfers to and from the card
- Extensive interrupt support system
- Adjustable clock rate and bit (baud) rate
- Configurable automatic byte repetition
- Handles commonly used communication protocols:
- T=0 for asynchronous half-duplex character transmission, and
- T=1 for asynchronous half-duplex block transmission
- Automatic convention detection
- Automatic voltage class selection
- Adjustable FIFOs for Receive and Transmit buffers (up to 32k characters) with threshold
- Configurable timing functions:
- Smart card activation time
- Smart card reset time
- Guard time
- Timeout timers
- Supports synchronous and any other non-ISO 7816 and non-EMV’96 or EMV2000 cards
- Standard system interface wrapper architecture for easy integration with host systems
- Fully-synchronous design suitable for scan-based testing
- Available in synthesizable HDL source code (versions for FPGAs also available)
Block Diagram
Specifications
Identity
Files
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Provider
Learn more about Smartcard IP core
Effective Optimization of Power Management Architectures through Four standard "Interfaces for the Distribution of Power"
Future Trends in SoC Interconnect
System-on-Chip Design using Self-timed Networks-on-Chip
SoC interfaces going 'soft'
More functions require balanced SoC design
Frequently asked questions about Smartcard IP cores
What is Smart Card Reader Controller?
Smart Card Reader Controller is a Smartcard IP core from CAST listed on Semi IP Hub.
How should engineers evaluate this Smartcard?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Smartcard IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.