Vendor: ASICS World Services, LTD. Category: I2C / I3C

I2C Master and Slave

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices.

Overview

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.

The interface defines 3 transmission speeds:

  • Normal: 100Kbps
  •  Fast: 400Kbps
  •  High speed: 3.5Mbps

Key features

  • Compatible with Philips I2C standard
  • Multimaster Operation
  • Software programmable clock frequency
  • Clock Stretching and Wait state generation
  • Software programmable acknowledge bit
  • Interrupt or bit-polling driven byte-by-byte data-transfers
  • Arbitration lost interrupt, with automatic switching from master to slave
  • Called as Slave interrupt
  • Start/Stop/Repeated Start generation
  • Acknowledge bit generation/detection
  • Start/Stop detection
  • Bus busy detection
  • Supports 7 and 10bit addressing mode in both master and slave modes
  • Operates from a wide range of input clock frequencies
  • Static synchronous design
  • Fully synthesizable

Specifications

Identity

Part Number
I2C
Vendor
ASICS World Services, LTD.
Type
Silicon IP

Files

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Provider

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Frequently asked questions about I2C / I3C IP cores

What is I2C Master and Slave?

I2C Master and Slave is a I2C / I3C IP core from ASICS World Services, LTD. listed on Semi IP Hub.

How should engineers evaluate this I2C / I3C?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this I2C / I3C IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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