JESD204 IP Listing

The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC) JESD204B standard.

• JESD204

JESD204 (Serial Interface for Data Convertors) is the serial communication protocol developed used with ADC and DAC.

• Verification IP

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces.

• JESD204

JESD204 CYCLIC FEC core is compliant with JESD204C version specification.Through its compatibility, it provides a simple interfac…

• JESD204

This JESD204 Verification IP provides an and efficient solution for verifying and debugging these standards in a UVM simulation e…

• Verification IP

The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inp…

• JESD204

Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol.

• Verification IP

The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…

• Single-Protocol PHY

Unleash the power of the new UCIe based RF Chiplet transceiver.

• TSMC
• 12nm
• FFC

Unleash the power of the new UCIe based RF Chiplet transceiver.

• TSMC
• 12nm
• FFC

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specif…

• JESD204

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specif…

• JESD204

JESD204C interface provides full support for the JESD204C synchronous serial interface,compatible with JESD204C version specifica…

• JESD204

JESD204C interface provides full support for the JESD204C synchronous serial interface,compatible with JESD204C version specifica…

• JESD204

The JESD204D Verification IP provides an effective & efficient way to verify the components (data converters and/or logic devices…

• Verification IP

Early adopter version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters The JESD204E Contro…

• JESD204

JESD207 RFIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant.

• JESD204

JESD207 BBIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant.

• JESD204

The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…

• UMC
• 28nm
• HPC

The multi-lane Multi-Protocol 16G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…

• UMC
• 28nm
• HPC