Vendor: NEXT Semiconductor Category: PLL

UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)

Unleash the power of the new UCIe based RF Chiplet transceiver.

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TSMC 12nm FFC View all specifications

Overview

Unleash the power of the new UCIe based RF Chiplet transceiver.

With NEXT Semiconductor's silicon proven 8-bit, 48-Gsps Transceiver, this product is ideal for moving from higher power consumption solutions based on JESD204 to the new UCIe interface.

NEXT Semiconductor was founded in 2004 by industry veterans who previously held managerial and technical leadership roles at Broadcom, Qualcomm, and NXP.

NEXT Semiconductor is a privately held corporation focused on the development of semiconductor products leveraging our novel DIGITAL DATA CONVERSION technology.

Key features

  • 48-Gsps peak sample rate
  • 8 bit resolution
  • UCIe SP (16x lanes at 16Gbps) with streaming controller
  • Usable RF Analog bandwidth up to 18 GHz
  • Up to 6.4 GHz of instantaneous bandwidth in 1 channel configuration or 3.2GHz in dual-channel configuration and 1.6GHz for the quad-channel solution
  • Multi-Chiplet phase synchronization
  • 4T4R silicon prototype evaluation system available (with JESD204 interface for easy evaluation on FPGA platforms)

Benefits

  • First in the market UCIe based RF Chiplet transceiver (4T4R)
  • Scalable solution for Multi-chip module (up to 8 RF Chiplets per package - 32T32R device)

Applications

  • Military and Aerospace: Radar, EW, EA, ISR, ELINT, Communications
  • Test and Measurement Equipment
  • Broadband Communication systems
  • Software defined radio
  • FPGA System-in-Package

What’s Included?

  • Datasheet
  • User guide
  • Customer Support
  • Package design support for achieving the best signal and power integrity
  • Evaluation board with software tool

Silicon Options

Foundry Node Process Maturity
TSMC 12nm FFC —

Specifications

Identity

Part Number
U1000
Vendor
NEXT Semiconductor
Type
Silicon IP

Provider

NEXT Semiconductor
HQ: United States
Contact NEXT Semiconductor

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe)?

UCIe based 8-bit 48-Gsps Transceiver (ADC/DAC/PLL/UCIe) is a PLL IP core from NEXT Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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