Vendor: SmartDV Category: JESD204

JESD207 RFIC IIP

JESD207 RFIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant.

Overview

JESD207 RFIC is full-featured, easy-to-use, synthesizable design, compatible with JESD207 Compliant. Through its JESD207 RFIC compatibility,it provides a simple interface to a wide range of low-cost devices. JESD204 RFIC IIP is proven in FPGA environment. The host interface of the JESD207 RFIC can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

JESD207 RFIC IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with JESD207 specification.
  • Full JESD207 RFIC functionality.
  • Supports half duplex data transfer.
  • Supports DDR source synchronous data transfer timing.
  • Supports both data path transactions and control plane transactions.
  • Supports data path transaction.
    • Supports transmit burst and receive burst.
    • Supports 12, 14 and 16 bits parallel data width.
    • Supports 2 way interleave and 4 way interleave transactions.
    • Supports 1T1R, 1T2R, 2T2R systems.
  • Supports to transmit and receive multiple parallel sample streams in data path interface
  • Supports control plane transaction.
    • Supports 4 wires write and 4 wires read.
    • Supports 3 wires write and 3 wires read.
    • 1bit command plus 7bit address control field format.
    • Serial clock can be stopped between transactions, reducing control plane power consumption to negligible levels.
    • Extended data transactions.
  • Fully synthesizable.
  • Static synchronous design.
  • No internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.

Block Diagram

JESD207 RFIC IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The JESD207 RFIC interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
JESD207 RFIC IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about JESD204 IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about JESD204 IP cores

What is JESD207 RFIC IIP?

JESD207 RFIC IIP is a JESD204 IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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