Vendor: SmartDV Category: JESD204

JESD204 Synthesizable Transactor

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces.

Overview

The JESD204 Synthesizable Transactor is compliant with JESD204 revision A/B/C specifications and verifies JESD204 interfaces. JESD204 is build on top of it to make it robust. JESD204 Synthesizable Transactor provides a smart way to verify the JESD204 component of a SOC or a ASIC in Emulator or FPGA platform.JESD204 Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.

Key features

  • Follows JESD204 specification JESD204A, JESD204B and JESD204C
  • Supports Transmitter and Receiver Mode
  • Supports up to 32 lanes
  • Supports 32bit data width per converter
  • Supports up to 32 converters per transmitter & receiver BFM
  • Scrambler can be enabled or disabled
  • Supports 8b/10b link layer functions
  • Supports 64b/66b link layer functions based on IEE802.3 Clause 49 and JESD204C
  • Supports 64b/80b link layer functions with fill bit encoding based on IEEE802.3 clause 49 and JESD204C
  • Supports Forward Error Correction (FEC), cyclic redundancy checks (CRC) and command channel
  • Supports single block, Multi block and extended multi block
  • Provides error injection and error detection with a wide variety of error types. Which includes:
    • Invalid code group insertion
    • Disparity errors
    • CRC errors
    • Sync error insertion
    • Lane skew insertion
    • FEC errors
    • Scrambler error insertion

Block Diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the JESD204 testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
JESD204 Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: India

Learn more about JESD204 IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about JESD204 IP cores

What is JESD204 Synthesizable Transactor?

JESD204 Synthesizable Transactor is a JESD204 IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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