Vendor: SmartDV Category: JESD204

JESD204B Receiver IIP

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specif…

Overview

JESD204B interface provides full support for the JESD204B synchronous serial interface,compatible with JESD204B.01 version specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. JESD204B Receiver IIP is proven in FPGA environment.The host interface of the JESD204B can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

JESD204B Receiver IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with JESD204 specification JESD204A, JESD204B.01.
  • Full JESD204B receive functionality.
  • Supports data rate upto 12.5 Gbps.
  • Supports programmable clock frequency up to 12.5 GHz.
  • Supports up to Subclass 0, 1, 2.
  • Supports up to Version A and B.
  • Supports 1 to 8 lanes.
  • Supports 1 to 8 converters per receiver.
  • Supports frame sizes of 1,2,4,8 and 16 octets per frame.
  • Supports HD-mode.
  • Supports 1 to 32 bit data width per converter.
  • Supports CF = 0 and 1 control words per frame clock period per link.
  • Supports 0 to 3 control bits per sample.
  • Supports 1 to 8 samples per converter.
  • Supports 1 to 32 frames per multiframe.
  • Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample.
  • Supports 0 to 15 bank ID – extension to DID.
  • Supports 0 to 255 device identification number.
  • Supports 0 to 7 lane identification number.
  • Supports reporting of various error statistics.
  • Supports different Serdes interfaces 10,20,40,60 bits and custom bits per lane.
  • Scrambler can be enabled or disabled.
  • Supports 10/8b decoding.
  • MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported.

Block Diagram

JESD204B Receiver IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The JESD204B Receiver interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
JESD204B Receiver IIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about JESD204 IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about JESD204 IP cores

What is JESD204B Receiver IIP?

JESD204B Receiver IIP is a JESD204 IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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