Vendor: Xilinx, Inc. Category: Single-Protocol PHY

JESD204 PHY

The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channel…

Overview

The Xilinx® LogiCORE™ IP JESD204 PHY core implements a JESD204B physical interface to simplify sharing serial transceiver channels between transmit and receive cores. This core is not intended to be used standalone and should only be used only in conjunction with the JESD204 core.

Note: This core is provided as standalone IP for use in the JESD204 IP example design only.

Key features

  • Designed to JEDEC® JESD204B
  • Supports 1 t0 12 lane configurations
  • Supports Subclass 0, 1, and 2
  • Physical layer functions provided
  • Supports trasceiver sharing between TX and RX cores

Specifications

Identity

Part Number
EF-DI-JESD204-SITE
Vendor
Xilinx, Inc.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about Single-Protocol PHY IP core

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Frequently asked questions about Single-Protocol PHY IP

What is JESD204 PHY?

JESD204 PHY is a Single-Protocol PHY IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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