Vendor: Cadence Design Systems, Inc. Category: JESD204

Simulation VIP for JESD204

Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol.

Contact Provider Request Datasheet
Verification IP View all specifications

Overview

Cadence provides a mature and comprehensive Verification IP (VIP) for the JESD204 protocol. Incorporating the latest protocol updates, the Cadence® Verification IP for JESD204 provides a complete bus functional model (BFM), integrated automatic protocol checks, and coverage model. Designed for easy integration in testbenches at IP, system-on-chip (SoC), and system levels, the VIP for JESD204 helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog verification language along with associated methodologies, including the Universal Verification Methodology (UVM).

Supported Specification: JESD204B and JESD204C

Key features

  • Topology
    • Transmitter or receiver configuration
  • Clock Frequency
    • Any frequency is supported, as the VIP works on the source clock
  • Initial Lane Alignment
    • Enabling or disabling initial lane alignment
  • Encoding Type
    • 8b10, 64b66b, and 64b80b encoding modes
  • 64-bit Sync Header
    • Transmission of all types of sync header information, such as, FEC, CRC-3, CRC-12 and command channel
  • Subclass
    • Subclass0, subclass1, and subclass2
  • Scrambling
    • Supports scrambling with user-specific initial seed value
  • Character Replacement
    • Character replacement feature with and without scrambling
  • Deterministic Delay
    • Deterministic delay for subclass 1 and 2
  • Transport Layer Parameter
    • Config/register to control transport layer features, such as CS, HD, and F
  • Lane Control
    • Lane ranging from 1 to 32
  • Lane to Lane Delay
    • Transmission and reception for cases where lanes are not aligned
  • Test Mode
    • Layer-wise test mode
  • Transport Layer Bypass
    • Skip transport layer operation like padding tail bits

Block Diagram

Simulation VIP for JESD204 block diagram

Specifications

Identity

Part Number
Simulation VIP for JESD204
Vendor
Cadence Design Systems, Inc.
Type
Verification IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Cadence Design Systems, Inc.

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is Simulation VIP for JESD204?

Simulation VIP for JESD204 is a JESD204 IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP