Vendor: SmartDV Technologies Category: JESD204

JESD204 CYCLIC FEC IIP

JESD204 CYCLIC FEC core is compliant with JESD204C version specification.Through its compatibility, it provides a simple interfac…

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Overview

JESD204 CYCLIC FEC core is compliant with JESD204C version specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. JESD204 CYCLIC FEC IIP is proven in FPGA environment.The host interface of the JESD204 CYCLIC FEC can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.

JESD204 CYCLIC FEC IIP is supported natively in Verilog and VHDL

Key features

  • Compliant with JESD204 specification JESD204C.
  • Supports Full JESD204C FEC functionality.
  • This FEC(Forward Error correction) methodology implements the (2074, 2048) binary cyclic code is shortened from the cyclic Fire code (8687, 8661).
  • Supports FEC of 26 bits parity bits.
  • Supports Error correct up to 9-bit burst error.
  • Supports the pipelined mechanism for the error correction.
  • FEC has a minimum latency of 58 blocks in the detection and correction of a bit error in the first scrambled data bit of a multiblock.

Block Diagram

JESD204 CYCLIC FEC IIP block diagram

Benefits

  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

What’s Included?

  • The JESD204 CYCLIC FEC interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases.
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files.
  • IP-XACT RDL generated address map.
  • Firmware code and Linux driver package.
  • Documentation contains User's Guide and Release notes.

Specifications

Identity

Part Number
JESD204 CYCLIC FEC IIP
Vendor
SmartDV Technologies
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact SmartDV Technologies

Learn more about JESD204 IP core

JESD204 Frame Mapping explained from converter samples to lanes

The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with ever increasing line rates, the function and features of the Transport Layer remained the same

Multiple ways JESD204 performs bitstream alignment

Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes.

Frequently asked questions about JESD204 IP cores

What is JESD204 CYCLIC FEC IIP?

JESD204 CYCLIC FEC IIP is a JESD204 IP core from SmartDV Technologies listed on Semi IP Hub.

How should engineers evaluate this JESD204?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this JESD204 IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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