The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate a…
- Hash / MAC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Helion Tiny Hash Core family for ASIC offers a combination of high functionality and low resource usage for lower data rate a…
The Helion ARC4 core implements the Alleged RC4 stream cipher algorithm.
The silicon proven USB host controller is compliant with USB 1.1 and OHCI 1.0 Specifications.
The USB 2.0 soft core facilitates data transmission up to 480 Mbps and is ideally suited for high-speed devices like CD-Rom drive…
x2 - 8-bit RISC Microcontroller
The DFPIC165X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast memory (typically …
CAN 2.0 B Compatible Network Controller
The logiCAN core provides all features expected from the standard CAN network controller.
The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
softDSP released 3GPP compliant Turbo decoder IP core in May, 2000.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
This is a high speed 8 state 3GPP™ (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible paralle…
Very High Speed 8 State MAP Decoder
This is a very high speed 8 state maximum a posteriori (MAP) soft-in-soft-out (SISO) triple interleaved error control decoder wit…
Universal Asynchronous Receiver / Transmitter
The macro M16550, implements a synchronous universal asynchronous receiver/transmitter, which provides an interface between a mic…
The USB2.0 PHY IP is a complete physical layer (PHY) IP solution designed for low power and peak performance.
Compliant to NIST FIPS PUB 197
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
Since its standardization of ISO/IEC 10918-1 in 1994, JPEG has been continued to be used as a still image storage format.
Baseline JPEG hardware IP compliant to the ISO/IEC 10918-1 standard as a very compact and high-speed compression IP
TMC’s frame rate converter uses an original frame interpolation technology and creates highly accurate interpolation frames with compact circuit resources.
H.264/AVC 1080 60p Baseline Profile Decoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)
H.264/AVC 1080 60p Baseline Profile Encoder - Intra-Only Version
Because of its compact design, it can be implemented in cheap FPGAs to reduce the costs. (e.g. CycloneV series, Artix7 series)