TSN GbE Ethernet switch / switched endpoint IP
IP
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
TSN GbE Ethernet switch / switched endpoint IP
IP
GbE automotive Ethernet/TSN switch IP with safety and security functions
IP
Wrapper IP building blocks for ES1 IP
IP
The Arm Cortex-M52 processor is the most area and energy efficient implementation of the Armv8.1-M architecture with Arm Helium v…
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC 12FFCP 1.8V, North/South Poly Orientation
The integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors,…
The vendor has designed LIN RTL IP Core, supporting data rate up to 20Kbps.
16Gbps and 10Gbps multi-protocol SerDes PHY
32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G The 32…
28G LR Multi-Protocol SerDes (MPS) PHY - Samsung 14nm
Optimized for power and area, our line-up of SerDes PHYs, delivering maximum performance and flexibility.
28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
Optimized for power and area, our line-up of SerDes PHYs, delivering maximum performance and flexibility.
Superscalar Out-of-Order Execution Multicore Cluster
AndesCore™ AX65 64-bit multicore CPU IP is a high-performance quad decode 13-stage superscalar out-of-order processor based on An…
LPDDR5X/5/4X PHY - TSMC N5A for Automotive, ASIL B Random, AEC-Q100 Grade 2
The LPDDR5X/5/4X PHY is a physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackag…
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
Tensilica DSP IP supports efficient AI/ML processing
The Cadence AI IP platform includes the extensible DSP platform from Cadence, which provides flexible instruction sets designed t…
The Cadence® Tensilica® NNE 110 offers an energy-efficient hardware-based AI engine that can be paired with a Tensilica based DSP.
The SiFive® Intelligence™ X288 is a multi-core capable processor extensively optimized to meet the harsh environmental and string…
High Performance RISC-V Processor for Edge Computing
Vector Instruction Set Support,Extended Vector Length Enhanced vector unit design optimized for machine learning workloads
Analog-PLL For Spread Spectrum Clock on TSMC 12nm
Analog-PLL For Spread Spectrum Clock on TSMC 7nm
Image warping IP (Distortion Correction IP)
Integrating coordinate transformation functions powered by GPU processing technologies. Distortion correction (any-shape transform), scaling, rotation.