3.2GHz Analog PLL for Spread Spectrum Clock Generator IP
3.2GHz analog phase-locked loop (PLL) IP for a spread spectrum clock generator (SSCG) using TSMC's 12nm FFC
Overview
The AT12CPLL0003SG3P2G18V1A is a 3.2GHz analog phase-locked loop (PLL) IP for a spread spectrum clock generator (SSCG) using TSMC's 12nm FFC (FinFET Compact) process technology.
Operating Condition
| Parameter | Min | Max | Unit |
|---|---|---|---|
| Operating Voltage (AVDD) | 1.6 | 1.98 | V |
| Operating Voltage (VDD) | 0.72 | 0.88 | V |
| Junction Temperature | -40 | 125 | °C |
| Input Clock — Duty | 20 | 80 | % |
| Input Clock — Rise / Fall time | - | 0.2 | ns |
Key features
- Includes a loop filter
- VCO operating range: 1600MHz to 3200MHz
- Output frequency range: 400MHz to 3200MHz
- Input frequency range: 10MHz to 200MHz
- Multiplying
- Output frequency/Input frequency: 2 to 320
- Fractional multiplying available
- SSC function available
- Modulation frequency
- 20kHz to 60kHz
- Modulation depth
- -1% to -6% down spread
- ±0.5% to ±3% center spread
- Modulation frequency
- Divider
- 33-bit feedback divider
- 3-bit input divider
- Power-down mode
- Process: TSMC 12nm FFC
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | Available on request |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about PLL IP cores
What is 3.2GHz Analog PLL for Spread Spectrum Clock Generator IP?
3.2GHz Analog PLL for Spread Spectrum Clock Generator IP is a PLL IP core from Renesas listed on Semi IP Hub. It is listed with support for tsmc Available on request.
How should engineers evaluate this PLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.