32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm

Designed to meet the power efficiency and performance requirements of next-generation, high-speed wireline and wireless 5G

The 32G MPS PHY is a comprehensive IP solution that is optimized for power and area in long-reach channels typical of communications, networking and data center applications. With high performance and multi-protocol compatibility, the PHY supports data rates from 2.5 to 32 Gbps in a wide range of industry-standard interconnect protocols including PCIe 4.0, JESD204B/C, CPRI and Ethernet. It features application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation. The 32G MPS PHY is designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features that maximize flexibility in today’s most challenging system environments. This makes the PHY ideal for high-performance wireline and 5G wireless infrastructure applications.

• Supports data rates of 2.5 to 32 Gbps
• Optimized for low-power operation and north/south die-edge placement
• AC-coupled RX front end with on-chip capacitors
• Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
• Duplex lane configurations of x4 and x1
• LC-PLLs provide a wide range of operating frequencies
• Wide range programmable multipliers for reference clock multiplication
• Differential reference clock inputs are selectively sourced from C4 or internal ASIC interface pins
• Flexible ASIC clocking
• Programmable clock outputs from the PLL to the ASIC core

• PMA hard macro and design kit
• Datasheet
• SoC integration guide
• Optional design integration and bring-up support services