Vendor: Cadence Design Systems, Inc. Category: Single-Protocol PHY

Low-Speed Ethernet SerDes

16Gbps and 10Gbps multi-protocol SerDes PHY

Overview

Cadence Ethernet SerDes IP solutions address the performance, power, and area requirements of today’s mobile, consumer, and enterprise (infrastructure) markets with extensive standard support for the latest PCI Express® (PCIe®), Ethernet and USB specifications. Available for both low-power mobile applications and high-performance computing applications, the Ethernet SerDes PHY IP is pre-integrated with Cadence controllers and equipped with extensive test features for superior interoperability and the lowest risk path to SoC success.

Key features

  • Wide range of protocols that support networking, HPC, and applications
  • Low-latency, long-reach, and low-power modes
  • Multi-Link PHY—mix protocols within the same macro
  • EyeSurf —non-destructive on-chip oscilloscope
  • Extensive set of isolation, test modes, and loop-backs including APB and JTAG
  • Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
  • Selectable serial pin polarity reversal for both transmit and receive paths

Block Diagram

Click to open fullscreen

Benefits

  • Low Power: Low-active and low-leakage optimized design
  • High Flexibility: Flexible lane configuration with multi-protocol multi-link support
  • Comprehensive Testability: Extensive testability support for BIST, scan, loopbacks, SoC isolation, and on-chip eye plotter

Specifications

Identity

Part Number
Low-Speed Ethernet SerDes
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Single-Protocol PHY IP core

Cadence Expands Sovereign AI in Europe: From Chips to AI Factories

To bring computing scale and regional data control together, Cadence is expanding its sovereign AI data center in Munich, becoming the first electronic design automation (EDA)opens in a new tab vendor to deliver a comprehensive sovereign AI platform for semiconductor, system, and AI factory design in Europe.

The Memory Challenge of Physical AI

As physical AI workloads become more complex, architects must now consider how predictably the complete system performs when multiple real-world workloads are active simultaneously.

PCI Express Security and TEE Integration, Part 1 - Establishing Trust

Protecting processor memory alone is no longer sufficient. The entire I/O path must become part of the trusted computing architecture. To address this challenge, PCI-SIG® has developed a suite of complementary security technologies, including Data Object Exchange (DOE), Component Measurement and Authentication (CMA), Integrity and Data Encryption (IDE), and the TEE Device Interface Security Protocol (TDISP).

Frequently asked questions about Single-Protocol PHY IP

What is Low-Speed Ethernet SerDes?

Low-Speed Ethernet SerDes is a Single-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP