Vendor: Cadence Design Systems, Inc. Category: Multi-Protocol PHY

28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm

Optimized for power and area, our line-up of SerDes PHYs, delivering maximum performance and flexibility.

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PHY GlobalFoundries 12nm LP In Production View all specifications

Overview

Optimized for power and area, our line-up of SerDes PHYs, delivering maximum performance and flexibility.

The 28 Gbps Multi-Protocol SerDes (MPS) PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical of networking and server systems. With high performance and multi-protocol compatibility, the PHYs support data rates from 1.25Gbps to 28.1Gbps across copper and backplane channels with more than 30dB channel insertion loss in a wide range of industry-standard interconnect protocols. They feature application-specific optimization enabled by an efficient and scalable architecture with adaptive and programmable receive equalization, and support for transmit FIR adaptation. The 28G MPS are designed with a system-oriented approach, taking the interface, interconnect and channel into account when optimizing performance and features to maximize flexibility in today's most challenging system environments and applications. This makes the PHYs ideal for many long-reach, copper and backplane enterprise environments.

Key features

  • Optimized for low-power operation and north/south die-edge placement
  • Duplex Lane configurations of x4 and x1
  • Adaptive receive equalizer with programmable settings providing up to 12dB of CTLE and 8-tap DFE support
  • An LC-PLL provides a wide range of operating frequencies
  • Embedded microcontroller for improved system configuration loads
  • Wide range programmable multipliers for reference clock multiplication
  • PHY is spec compliant across a wide operating junction temperature range (-20 °C to 125 °C). PLLs, bias circuits, and data path are functional between -40 °C to -20 °C
  • Built-in Self Test (BIST) support
  • Built-in PRBS15/31 and custom pattern generation and checking for standalone testing

What’s Included?

  • PMA Hard Macro
  • Datasheet
  • SoC integration guide
  • Optional design integration and bring-up support services

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 12nm LP In Production

Specifications

Identity

Part Number
28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm
Vendor
Cadence Design Systems, Inc.
Type
Silicon IP
Controller / PHY
PHY

Provider

Contact Cadence Design Systems, Inc.

Learn more about Multi-Protocol PHY IP core

How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity

Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.

Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Modern compute systems have evolved beyond reliance on a single dominant interface. Today, they're increasingly defined by their ability to support multiple high-speed protocols concurrently—including PCIe, Ethernet, and others. This shift toward multi-protocol capability is fundamentally reshaping how we architect intelligent edge AI systems, especially as inferencing workloads grow more distributed, data-intensive, and latency-sensitive.

Frequently asked questions about Multi-Protocol PHY IP cores

What is 28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm?

28G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 12nm is a Multi-Protocol PHY IP core from Cadence Design Systems, Inc. listed on Semi IP Hub. It is listed with support for globalfoundries In Production.

How should engineers evaluate this Multi-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Multi-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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