Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and …
- Channel Coding
- MVP RTL, Verified
- Now
- 5G DVBS2 802.11n
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and …
The Tessent Embedded Analytics solution can be used to produce health and operational metrics throughout the lifecycle of an SoC.
Tessent Automotive IC debug and optimization
Vehicles are becoming complex systems approaching billions of lines of code.
Tessent AI IC debug and optimization
The multicore architectures of SoCs for machine learning (ML) and artificial intelligence (AI) applications provide unique challe…
Tessent Static Instrumentation
The Tessent Embedded Static Instrumentation module provides a nonintrusive mechanism for code instrumentation.
Tessent SoC debug and optimization
Tessent Embedded Analytics accelerates debug, validation, and optimization of complex multi-core SoCs.
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).
Process voltage and temperature detection of the silicon chip die is accomplished by PVT Sensor, an IP.
SOQPSK-TG LDPC Modulator for communication systems with non-linear amplifiers
The IPrium-SOQPSK-LDPC-Modulator IP Core implements constant amplitude CPM SOQPSK modulation with LDPC Coding.
Low Dropout (LDO) Capless Regulator 250mA - TSMC 40
1-VIA’s Linear Low-Dropout (LDO) voltage regulator IP is a capless LDO regulator which provides programmable precise voltage regu…
Configurable CAN Bus Controller with Flexible Data-Rate
CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL.
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital…
ECDSA signature verification engine
In addition to its support for various elliptic curves, CryptOne’s prowess extends to the widely acclaimed Elliptic Curve Digital…
high-performance solution for elliptic curve cryptography
Our ECC IP Core represents a cutting-edge solution that brings the power of elliptic curve cryptography to your systems.
128x1 Bits OTP (One-Time Programmable) IP, UMC 0.18um 1.8V/5V BCD Process
The ATO00128X1UM180B502NA is organized as a 128-bit by 1 one-time programmable (OTP).
256x1 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
The AT256X1U110MAE0AB is organized as 256 bits by 1 one-time programmable in 1-bit read and 1-bit program modes.
512x1 Bits OTP (One-Time Programmable) IP, UMC 0.18um 1.8V/5V BCD Process
The ATO00512X1UM180B502NA is organized as a 512-bit by 1 one-time programmable (OTP).
256x16 Bits OTP (One-Time Programmable) IP, TSMC 152nm 1.8V/3.3V GP MS Process
The AT256X16T152LP0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes.
128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process
The AT128X16B130XR0BA is organized as 128 words by 16 bits one-time programmable in 16-bit read and 1-bit program modes.