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Vendor:
Synopsys, Inc.
Category:
CPU
ARC-V RMX-100 Processor IP
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern.
Overview
The ARC-V™ RMX-100 series processors are optimized for use in embedded applications where power and area are the utmost concern. The DSP enhanced implementation (RMX-100D) adds DSP capability for applications such as hearable devices where the combination of low power and signal processing are required to enable device performance and extend battery life.
The ARC-V RMX-100 processors are based on the RISC-V instruction set architecture (ISA) and feature a balanced 3-stage Harvard architecture pipeline that provides sufficient throughput. The ARC-V RMX-100 features up to 64KB of level 1 (L1) instruction cache and up to 2MB each of closely coupled instruction and data memories (CCM).
The DSP-enhanced RMX-100D cores include an optimized DSP implementation that features a power-efficient unified 32x32 MUL/MAC unit and support for fixed-point DSP datatypes and vector operations. To enable easy DSP software development, the ARC MetaWare Development Toolkit features a rich DSP software library and the included C/C++ Compiler supports commonly used DSP datatypes for easy algorithm programming. The ARC-V RMX-100D processors maintain the high code density and offer excellent DSP performance within a very small footprint.
To maximize PPA of ARC-V RMX Processor-based designs, a Fusion QuickStart Implementation Kit (QIK) that includes tool scripts, a baseline floorplan, design constraints and documentation, is available.
Key features
- Family of 32-bit RISC processors for ultra-low power embedded applications
- Based on the RISC-V ISA, leveraging standard 32-bit protocols (and extensions)
- DSP instruction extensions (RMX-100D)
- Easy DSP programming support with MetaWare C/C++ Compiler (RMX-100D)
- Feature-rich DSP software library for easy algorithm programming
- High degree of configurability
- Support for custom instructions
- Support for up to 2 MB of closely coupled memory and direct mapping of peripherals
- Native Arm AMBA® AHB™, AHBLite™ and AXI interfaces
- Optional 32x32 or 16x16 single and multicycle multiplier
- ECC/Parity support
- RISC-V AIA compatible interrupt handling architecture
- Advanced Platform Level Interrupt Controller (APLIC) supporting up to 1023 wired interrupts
- ARC Trace I/F provides real-time trace debugging features
Block Diagram
arc-v-rmx-100 block diagram
Benefits
- RMX-100
- Ultra-low power 32-bit RISC-V cores
- Targeting embedded applications where minimal power & area consumption is essential
- RMX-100D
- Ultra-low power 32-bit RISC-V cores with DSP
- Over 150 DSP extension instructions
- Easy DSP programming support
Specifications
Identity
Part Number
arc-v-rmx-100
Vendor
Synopsys, Inc.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about CPU IP cores
What is ARC-V RMX-100 Processor IP?
ARC-V RMX-100 Processor IP is a CPU IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.