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Vendor:
Synopsys, Inc.
Category:
Single-Protocol PHY
1.6T Ethernet PCS IP
The 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution…
Overview
The 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution for next generation 400Gbps and 800Gbps and 1.6Tbps Ethernet applications. It operates over 16 serial lanes of 106.25Gbps for 1.6T. The additional specific Physical Media Attachment (PMA) layer transparently multiplexes two lanes to support >=212.5Gbps SerDes lanes.
The 1.6T Ethernet PCS IP seamlessly interoperates with the 1.6T Ethernet MAC IP and the 224G Ethernet PHY IP to provide a complete Ethernet MAC, PCS and PHY solution for 1.6T systems. The 1.6T PCS sublayer couples the 802.3 MAC to a family of 1.6Tbps Physical Layers.
Key features
- Supports all required features of the IEEE 802.3 specification and draft specifications
- IP available in single 1.6T mode and quad channel mode supporting 4 x 400G, 2 x 800G and 1.6T
- Designed to be used with Synopsys 1.6T MAC IP for 1.6T Ethernet Systems
- Includes RS-FEC functions
- Integration tested with the 1.6T Ethernet
- MAC and 224G Ethernet PHY IP
Block Diagram
dw_1_6t_ethernet_pcs_ip block diagram
Benefits
- The PMA service interface per lane operates with a transfer rate of 106.25Gbps per lane
- The PCS Client Interface implements a 1600GMII conceptually identical to the 200GMII/400GMII of 802.3 Clause 119
- The PCS implements Reed-Solomon Forward Error Correction (RS-FEC). The RS-FEC implements the RS(544,514) as defined in IEEE 802.3 using codeword interleaving
- The RS-FEC supports external statistics collection by providing a statistics vector which provides information for codewords, corrected codewords, uncorrected codewords as well as individual symbols corrected per codeword if corrections occurred. Option to integrate RS-FEC Statistics module
- Pseudo-random test-pattern generator and checker for transmiter and receiver testing
- Fault detection capable of indicating faults that render a link unreliable (loss of synchronization or excessive bit errors)
- Generic host interface allowing direct access to all configuration and status registers
- Multi-channel support with support for 4 * 400G (802.3 Clause 119) and 2 * 800G (Draft 802.3df) and 1.6T (Draft 802.3dj)
- Optional single channel 1.6T PCS.
Specifications
Identity
Part Number
dw_1_6t_ethernet_pcs_ip
Vendor
Synopsys, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about Single-Protocol PHY IP
What is 1.6T Ethernet PCS IP?
1.6T Ethernet PCS IP is a Single-Protocol PHY IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.