The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…
- UCIe
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and mai…
Low Pin Count (LPC) controller verification IP
The Low Pin Count (LPC) interface is a low bandwidth bus with up to 33 MHz performance.
The vendor provides configurable GDDR6 verification IP.
The TS5111 and TS5110 device incorporate thermal sensing capability which is controlled and read over two wire bus.
The vendor provides configurable CPRI TX/RX verification IP.
Hierarchical scalability is the foundation principle of the Fibonacci machine-learning (ML) system-on-chip (SoC).
Ultra-low-power 60 GHz radar-on-chip
Short-range radar has many potential applications, such as gesture control, contactless vital-signs monitoring, presence detectio…
APB to AHB-Lite Asynchronous Bridge
The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB Lite bus …
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction.
The AHB SRAM Controller provides a standard AHB interface to translate AHB bus reads and writes into reads and writes with the si…
The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface.
The Encryption Standard (AES) IP Core is a hardware implementation encryption/decryption algorithm described in the U.S.
AXI 5-Master Component Low-Latency SRAM Controller
The AXI 5-Master component SRAM Controller provides 5 AXI 64-bit Master components with low-wait-state access to a single interna…
12-bit 2GSPS Time Interleaved ADC
The WEAADC12BHSI22G is a 12-bit timeinterleaved Successive Approximation Analog-toDigital Converter (ADC) that supports both sing…
12-bit High Speed Analog to Digital Converter
The WEAADC12BHS22G is a 12-bit Successive Approximation Analog-to-Digital Converter (ADC) that supports both single-ended and dif…
The CMS-1 is a parameterized integration of the VSC-1 scaler core with other IP as needed for ABR and similar applications requir…
The XC23 is the most DSP core available today for communications applications.
HDLC frame to APB bridge , is cable of receive and transmit of HDLC frame .
The USB Host, as defined by the OHCI specification, is a hardware controller designed to manage communication between a host syst…
The CryptoManager RT-6xx v3 Root of Trust family from Rambus is the latest generation of fully programmable FIPS 140-3 compliant …