Vendor: Weasic Microelectronics Category: ADC

12-bit 2GSPS Time Interleaved ADC

The WEAADC12BHSI22G is a 12-bit timeinterleaved Successive Approximation Analog-toDigital Converter (ADC) that supports both sing…

12 Bit GlobalFoundries 22nm FDX View all specifications

Overview

The WEAADC12BHSI22G is a 12-bit time

interleaved Successive Approximation Analog-toDigital Converter (ADC) that supports both singleended and differential operation, depending on the

input and reference connections. It integrates 13

WEAADC12BHS22G with programmable clock

skew (50ps coarse 4ps fine with minimum step

0.25ps) and pre/post-calibration logic on each.

Operating on a 0.8 V power supply, the

WEAADC12BHSI22G can provide output up to

2GSPS in 13-interleaved mode. The ADC can be

clocked with 2GHz clock. Each ADC resolution is

programmable from 8 to 12 bits, as well as the

overall amount of interleaved instances

Key features

  • Supply Voltage (typ) : 0.8 V
  • Resolution : 12 bits
  • Conversion rate : 2 GSPS
  • Vin : 0.25 V to 0.75 V
  • Vin diff : 500 mV
  • Vcm: 500 mV
  • INL : 1.1 LSB (typ)
  • DNL: ±0.85 LSB (typ)
  • ENOB: 10.5
  • Area: 1.5 mm2

Block Diagram

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 22nm FDX

Specifications

Identity

Part Number
WEAADC12BHSI22G
Vendor
Weasic Microelectronics
Type
Silicon IP

Analog

Resolution bits
12 Bit

Files

Note: some files may require an NDA depending on provider policy.

Provider

Frequently asked questions about ADC IP cores

What is 12-bit 2GSPS Time Interleaved ADC?

12-bit 2GSPS Time Interleaved ADC is a ADC IP core from Weasic Microelectronics listed on Semi IP Hub. It is listed with support for globalfoundries.

How should engineers evaluate this ADC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ADC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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