The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…
- Channel Coding
The Viterbi Intel FPGA IP core generates high-performance, soft-decision Viterbi intellectual property (IP) functions that implem…
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
LTE Viterbi Decoder
16-ACS Multi Function Viterbi Decoder
The VA08VB is a medium complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
16 State DVB-S2/DVB-S2X Tail Biting Viterbi Decoder
The VA04D is a 16 state tail-biting error control decoder using the maximum likelihood Viterbi algorithm.
Lattice's Viterbi Decoder is a parameterizable IP core with an efficient algorithm for decoding different combinations of convolu…
Multi Function Viterbi Decoder
The VA08VA is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction.
64/256 state block Viterbi decoder
The VA08S is a low complexity 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
Viterbi Decoders are used in systems where data are transmitted and subject to errors before reception.
The VA08V is a low complexity 16, 32, 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
The IPrium-Viterbi-Decoder IP Core implements Viterbi decoding algorithm and supports trellis mode of operattion.
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications.