The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize cl…
- DLL
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The (Delay-Locked Loop) DLL PHY is a mix-signal circuit used in low-power and high-speed applications to align and synchronize cl…
The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity…
Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processor…
USB 3.1/DisplayPort 1.3 Controller IP Solutions
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1/DisplayPort 1.4 IP Subsystem Solution
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
Ultra High-Performance AES-GCM/CTR IP
The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence i…
True Random Number Generator for NIST SP 800-90c
The security strength of many systems and applications is dependent on the quality of random number generators.
Security Protocol Accelerator for SM3 and SM4
SM3 and SM4 are commercial cryptographic standards issued and regulated by the Chinese Office of State Commercial Cryptography Ad…
Multipurpose Security Protocol Accelerator
Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer.
High-Performance AES-XTS/ECB IP
Memory and storage security involves protecting storage resources and the data stored on them, both on-premises and in external d…
High-Performance AES-GCM/CTR IP
The compact, high-performance Synopsys Pipelined AES-GCM/CTR Core implements the AES-GCM/CTR algorithm as specified in the Nation…
Embedded Security Modules for HDCP 2.3 on HDMI IP
The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are solutions that pr…
HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
The Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are solutions that provide des…
Multiport/Multiprotocol HDCP 2.3 Embedded Security Modules
The Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are solutions that provide des…
MIPI C/D-PHY CSI/DSI TX and RX
The MIPI C/D-PHY + DSI/CSI Controller IP is a versatile solution designed for high-speed data transmission in mobile and multimed…
The M-PHY implements MIPI M-PHY protocol V4.1.
The LVDS implements LVDS TIA/EIA protocol, providing a low-voltage, high-speed point-to-point signal interface.
The Audio CODEC IP is a low power, high resolution, stereo audio solution which leverages Sigma-Delta noise-shaping technology.
High performance FFT with Gsps throughput
The eSi-FFT-Gsps is an FFT design tailored for high-throughput applications, specifically design to seamlessly integrate with hig…
Ultra-Low-Power Bandgap Voltage Reference in 40nm CMOS
The ODT-REF-SV1P8-ULP140N_40 is an ultralow power CMOS bandgap reference designed in a 40nm standard CMOS process without needing…